International Symposium on High Performance Computer Architecture
HPCA
A*
CORE rank
CORE rank (raw)
A*
Fields of research
Computer Systems Engineering · Distributed Computing and Systems Software
Papers indexed
1,671
1995–2026
Papers per year
1995122 peak2026
Most published authors
HPCA papers
1,671 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2013 | Coset coding to extend the lifetime of memory. | Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin |
| 2013 | Cost effective data center servers. | Rui Hou, Tao Jiang, Liuhang Zhang, Pengfei Qi, Jianbo Dong, Haibin Wang, Xiongli Gu, Shujie Zhang |
| 2013 | Disintegrated control for energy-efficient and heterogeneous memory systems. | Tae Jun Ham, Bharath K. Chelepalli, Neng Xue, Benjamin C. Lee |
| 2013 | Navigating heterogeneous processors with market mechanisms. | Marisabel Guevara, Benjamin Lubin, Benjamin C. Lee |
| 2013 | Power-performance co-optimization of throughput core architecture using resistive memory. | Nilanjan Goswami, Bingyi Cao, Tao Li |
| 2013 | Power-efficient computing for compute-intensive GPGPU applications. | Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte |
| 2013 | Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches. | Muhammad Umar Farooq, Khubaib, Lizy K. John |
| 2013 | Application-to-core mapping policies to reduce memory system interference in multi-core systems. | Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi |
| 2013 | Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors. | Neal Clayton Crago, Omid Azizi, Steven S. Lumetta, Sanjay J. Patel |
| 2013 | Worm-Bubble Flow Control. | Lizhong Chen, Timothy Mark Pinkston |
| 2013 | Technology comparison for large last-level caches (L | Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob |
| 2013 | TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. | Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King |
| 2013 | Runnemede: An architecture for Ubiquitous High-Performance Computing. | Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benot Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu |
| 2013 | Two level bulk preload branch prediction. | James Bonanno, Adam Collura, Daniel Lipetz, Ulrich Mayer, Brian R. Prasky, Anthony Saporito |
| 2013 | Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. | Emily R. Blem, Jaikrishnan Menon, Karthikeyan Sankaralingam |
| 2013 | High-speed formal verification of heterogeneous coherence hierarchies. | Jesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte |
| 2013 | ECM: Effective Capacity Maximizer for high-performance compressed caching. | Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Junghee Lee, Jongman Kim |
| 2013 | ESESC: A fast multicore simulator using Time-Based Sampling. | Ehsan K. Ardestani, Jose Renau |
| 2013 | Illusionist: Transforming lightweight cores into aggressive cores on demand. | Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke |
| 2013 | Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. | Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas |
| 2013 | A group-commit mechanism for ROB-based processors implementing the X86 ISA. | Furat Afram, Hui Zeng, Kanad Ghose |
| 2013 | Scaling towards kilo-core processors with asymmetric high-radix topologies. | Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge |
| 2013 | Warped register file: A power efficient register file for GPGPUs. | Mohammad Abdel-Majeed, Murali Annavaram |
| 2012 | AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. | Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang |
| 2012 | CPU-assisted GPGPU on fused CPU-GPU architectures. | Yi Yang, Ping Xiang, Mike Mantor, Huiyang Zhou |
1,026–1,050 of 1,671← PreviousNext →
Comparable venues
Other A*/A conferences filed under the same field of research.
- ADATEDesign, Automation and Test in Europe Conference
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- AITCIEEE International Test Conference
- A*ISCAACM International Symposium on Computer Architecture
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design