| 2007 | Modeling and Managing Thermal Profiles of Rack-mounted Servers with ThermoStat. | Jeonghwan Choi, Youngjae Kim, Anand Sivasubramaniam, Jelena Srebric, Qian Wang, Joonwon Lee |
| 2007 | An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing. | Liqun Cheng, John B. Carter, Donglai Dai |
| 2007 | A Scalable, Non-blocking Approach to Transactional Memory. | Hassan Chafi, Jared Casper, Brian D. Carlstrom, Austen McDonald, Chi Cao Minh, Woongki Baek, Christos Kozyrakis, Kunle Olukotun |
| 2007 | Colorama: Architectural Support for Data-Centric Synchronization. | Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas |
| 2007 | Implications of Device Timing Variability on Full Chip Timing. | Murali Annavaram, Ed Grochowski, Paul Reed |
| 2007 | Interactions Between Compression and Prefetching in Chip Multiprocessors. | Alaa R. Alameldeen, David A. Wood |
| 2007 | Exploiting Postdominance for Speculative Parallelization. | Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone, Matthew I. Frank |
| 2006 | High performance file I/O for the Blue Gene/L supercomputer. | Hao Yu, Ramendra K. Sahoo, C. Howson, George Almsi, Jos G. Castaos, Manish Gupta, Jos E. Moreira, Jeffrey J. Parker, Thomas Engelsiepen, Robert B. Ross, Rajeev Thakur, Robert Latham, William D. Gropp |
| 2006 | Industrial Perspectives: Platform Design Challenges with Many cores. | Raj Yavatkar |
| 2006 | Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. | Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg |
| 2006 | Store vectors for scalable memory dependence prediction and scheduling. | Samantika Subramaniam, Gabriel H. Loh |
| 2006 | Chip-multiprocessing and beyond. | Per Stenstrm |
| 2006 | InfoShield: a security architecture for protecting information usage in memory. | Weidong Shi, Joshua B. Fryman, Guofei Gu, Hsien-Hsin S. Lee, Youtao Zhang, Jun Yang |
| 2006 | New architectures for a new biology. | Doug E. Shaw |
| 2006 | Efficient instruction schedulers for SMT processors. | Joseph J. Sharkey, Dmitry V. Ponomarev |
| 2006 | Probabilistic counter updates for predictor hysteresis and stratification. | Nicholas Riley, Craig B. Zilles |
| 2006 | Industrial Perspectives: System IO Network Evolution - Closing Requirement Gaps. | Renato Recio |
| 2006 | Increasing the cache efficiency by eliminating noise. | Prateek Pujara, Aneesh Aggarwal |
| 2006 | CORD: cost-effective (and nearly overhead-free) order-recording and data race detection. | Milos Prvulovic |
| 2006 | A decoupled KILO-instruction processor. | Miquel Perics, Adrin Cristal, Rubn Gonzlez, Daniel A. Jimnez, Mateo Valero |
| 2006 | Exploiting parallelism and structure to accelerate the simulation of chip multi-processors. | David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors |
| 2006 | DMA-aware memory energy management. | Vivek Pandey, Weihang Jiang, Yuanyuan Zhou, Ricardo Bianchini |
| 2006 | ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. | Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas |
| 2006 | LogTM: log-based transactional memory. | Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, David A. Wood |
| 2006 | Completely verifying memory consistency of test program executions. | Chaiyasit Manovit, Sudheendra Hangal |