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International Symposium on High Performance Computer Architecture

HPCA

A*

CORE rank

CORE rank (raw)

A*

Fields of research

Computer Systems Engineering · Distributed Computing and Systems Software

Papers indexed

1,671

1995–2026

Papers per year

1995122 peak2026

HPCA papers

1,671 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2002Thread-Spawning Schemes for Speculative Multithreading.Pedro Marcuello, Antonio Gonzlez
2002The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.Martin Kmpe, Per Stenstrm, Michel Dubois
2002CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters.Peter Jamieson, Angelos Bilas
2002Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach.Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John
2002Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation.Ed Grochowski, David Ayers, Vivek Tiwari
2002Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors.Marcelo H. Cintra, Josep Torrellas
2002The Software Industry: Ten Lessons for Long Life.Timothy Chou
2002Tuning Garbage Collection in an Embedded Java Environment.Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
2002Evaluation of a Multithreaded Architecture for Cellular Computing.Calin Cascaval, Jos G. Castaos, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, Jos E. Moreira, Karin Strauss, Henry S. Warren Jr.
2002User-Level Communication in Cluster-Based Servers.Enrique V. Carrera, Srinath Rao, Liviu Iftode, Ricardo Bianchini
2002Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.Mary D. Brown, Yale N. Patt
2002Loose Loops Sink Chips.Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer
2001A Programmable Co-Processor for Profiling.Craig B. Zilles, Gurindar S. Sohi
2001An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
2001Register Renaming and Scheduling for Dynamic Execution of Predicated Code.Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
2001Dynamic Prediction of Critical Path Instructions.Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder
2001Self-Tuned Congestion Control for Multiprocessor Networks.Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee
2001Branch History Guided Instruction Prefetching.Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
2001Speculative Data-Driven Multithreading.Amir Roth, Gurindar S. Sohi
2001Towards Virtually-Addressed Memory Hierarchies.Xiaogang Qiu, Michel Dubois
2001A Delay Model and Speculative Architecture for Pipelined Routers.Li-Shiuan Peh, William J. Dally
2001JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers.Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary
2001Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors.Pierre Michaud, Andr Seznec
2001Reducing DRAM Latencies with an Integrated Memory Hierarchy Design.Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
2001Automatically Mapping Code on an Intelligent Memory Architecture.Jaejin Lee, Yan Solihin, Josep Torrellas
1,4261,450 of 1,671← PreviousNext →

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