| 2000 | A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. | Henk Neefs, Hans Vandierendonck, Koenraad De Bosschere |
| 2000 | High-Throughput Coherence Controllers. | Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph |
| 2000 | Software-Controlled Multithreading Using Informing Memory Operations. | Todd C. Mowry, Sherwyn R. Ramkissoon |
| 2000 | Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. | Andreas Moshovos, Gurindar S. Sohi |
| 2000 | Design of a Parallel Vector Access Unit for SDRAM Memory Systems. | Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis |
| 2000 | Reducing Code Size with Run-Time Decompression. | Charles Lefurgy, Eva Piccininni, Trevor N. Mudge |
| 2000 | Decoupled Value Prediction on Trace Processors. | Sang Jeong Lee, Yuan Wang, Pen-Chung Yew |
| 2000 | Coherence Communication Prediction in Shared-Memory Multiprocessors. | Stefanos Kaxiras, Cliff Young |
| 2000 | A Prefetching Technique for Irregular Accesses to Linked Data Structures. | Magnus Karlsson, Fredrik Dahlgren, Per Stenstrm |
| 2000 | eXtended Block Cache. | Stphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen |
| 2000 | On the Performance of Hand vs. Automatically Optimized Numerical Codes. | Marta Jimnez, Jos M. Llabera, Agustn Fernndez |
| 2000 | A DSM Architecture for a Parallel Computer Cenju-4. | Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose |
| 2000 | Branch Transition Rate: A New Metric for Improved Branch Classification Analysis. | Michael Haungs, Phil Sallee, Matthew K. Farrens |
| 2000 | Impact of Heterogeneity on DSM Performance. | Renato J. O. Figueiredo, Jos A. B. Fortes |
| 2000 | Cache Memory Design for Network Processors. | Tzi-cker Chiueh, Prashant Pradhan |
| 2000 | Cache-Efficient Matrix Transposition. | Siddhartha Chatterjee, Sandeep Sen |
| 2000 | Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks. | Rafael Casado, Aurelio Bermdez, Francisco J. Quiles, Jos L. Snchez, Jos Duato |
| 2000 | Investigating the Performance of Two Programming Models for Clusters of SMP PCs. | Franck Cappello, Olivier Richard, Daniel Etiemble |
| 2000 | Dynamic Cluster Assignment Mechanisms. | Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonzlez |
| 2000 | Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight? | James Burns, Jean-Luc Gaudiot |
| 2000 | Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study. | Robert P. Bosch Jr., Chris Stolte, Gordon Stoll, Mendel Rosenblum, Pat Hanrahan |
| 2000 | PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620. | Peter M. Behr, S. Pletner, Angela C. Sodan |
| 2000 | Impact of Chip-Level Integration on Performance of OLTP Workloads. | Luiz Andr Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese |
| 1999 | Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. | Ye Zhang, Lawrence Rauchwerger, Josep Torrellas |
| 1999 | Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks. | Yuanyuan Yang, Jianchao Wang |