| 2011 | CoreRacer: a practical memory race recorder for multicore x86 TSO processors. | Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu |
| 2011 | Formally enhanced runtime verification to ensure NoC functional correctness. | Ritesh Parikh, Valeria Bertacco |
| 2011 | FeatherWeight: low-cost optical arbitration with QoS support. | Yan Pan, John Kim, Gokhan Memik |
| 2011 | Resilient microring resonator based photonic networks. | Christopher Nitta, Matthew K. Farrens, Venkatesh Akella |
| 2011 | CRAM: coded registers for amplified multiporting. | Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti |
| 2011 | Improving GPU performance via large warps and two-level warp scheduling. | Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt |
| 2011 | Reducing memory interference in multicore systems via application-aware memory channel partitioning. | Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda |
| 2011 | Packet chaining: efficient single-cycle allocation for on-chip networks. | George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally |
| 2011 | Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip. | Debora Matos, Gianluca Palermo, Vittorio Zaccaria, Cezar Reinbrecht, Altamiro Amadeu Susin, Cristina Silvano, Luigi Carro |
| 2011 | Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations. | Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa |
| 2011 | Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. | Gabriel H. Loh, Mark D. Hill |
| 2011 | A register-file approach for row buffer caches in die-stacked DRAMs. | Gabriel H. Loh |
| 2011 | System-level integrated server architectures for scale-out datacenters. | Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi |
| 2011 | Active management of timing guardband to save energy in POWER7. | Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, Jos A. Tierno, John B. Carter |
| 2011 | Idempotent processor architecture. | Marc de Kruijf, Karthikeyan Sankaralingam |
| 2011 | Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication. | Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt |
| 2011 | Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. | Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong |
| 2011 | Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. | Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John |
| 2011 | BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. | John Jose, J. Shiva Shankar, K. V. Mahathi, Damarla Kranthi Kumar, Madhu Mutyam |
| 2011 | Architectural support for secure virtualization under a vulnerable hypervisor. | Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh |
| 2011 | B2RAC: a physical express link addition methodology for network on chip. | Jiajia Jiao, Yuzhuo Fu |
| 2011 | Complementing user-level coarse-grain parallelism with implicit speculative parallelism. | Nikolas Ioannou, Marcelo Cintra |
| 2011 | Floodgate: application-driven flow control in network-on-chip for many-core architectures. | Yoshi Shih-Chieh Huang, Huan-Yu Liu, Yuan-Ying Chang, Chung-Ta King, Shau-Yin Tseng |
| 2011 | Preventing PCM banks from seizing too much power. | Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger |
| 2011 | The NoX router. | Mitchell Hayenga, Mikko H. Lipasti |