Skip to content

International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2007Impact of Cache Coherence Protocols on the Processing of Network Traffic.Amit Kumar, Ram Huggahalli
2007Composable Lightweight Processors.Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
2007Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe
2007Flattened Butterfly Topology for On-Chip Networks.John Kim, James D. Balfour, William J. Dally
2007Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.Stephen Hines, David B. Whalley, Gary S. Tyson
2007A Framework for Providing Quality of Service in Chip Multi-Processors.Fei Guo, Yan Solihin, Li Zhao, Ravishankar R. Iyer
2007Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs.Mrinmoy Ghosh, Hsien-Hsin S. Lee
2007Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow.Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt
2007Microarchitectural Design Space Exploration Using an Architecture-Centric Approach.Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle
2007Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation.Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco
2007Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures.Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke
2007Informed Microarchitecture Design Space Exploration Using Workload Dynamics.Chang-Burm Cho, Wangyuan Zhang, Tao Li
2007Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications.Yuan Chou
2007FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators.Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
2007Revisiting the Sequential Programming Model for Multi-Core.Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. August
2007Self-calibrating Online Wearout Detection.Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
2007Scavenger: A New Last Level Cache Architecture with Global Block Priority.Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jos F. Martnez
2007Penelope: The NBTI-Aware Processor.Jaume Abella, Xavier Vera, Antonio Gonzlez
2006Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection.Xiaotong Zhuang, Tao Zhang, Santosh Pande
2006Memory Protection through Dynamic Access Control.Kun Zhang, Tao Zhang, Santosh Pande
2006Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units.Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
2006Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions.Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell
2006Scalable Cache Miss Handling for High Memory-Level Parallelism.James Tuck, Luis Ceze, Josep Torrellas
2006Adaptive Caches: Effective Shaping of Cache Behavior to Workloads.Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh
2006Fire-and-Forget: Load/Store Scheduling with No Store Queue at All.Samantika Subramaniam, Gabriel H. Loh
1,4261,450 of 2,401← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.