| 2008 | Evaluating the effects of cache redundancy on profit. | Abhishek Das, Berkin zisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary |
| 2008 | Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. | Kypros Constantinides, Onur Mutlu, Todd M. Austin |
| 2008 | Shapeshifter: Dynamically changing pipeline width and speed to address process variations. | Eric Chun, Zeshan Chishti, T. N. Vijaykumar |
| 2008 | Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. | Xi E. Chen, Tor M. Aamodt |
| 2008 | Power reduction of CMP communication networks via RF-interconnects. | M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam |
| 2008 | Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. | Ramazan Bitirgen, Engin Ipek, Jos F. Martnez |
| 2008 | Low-power, high-performance analog neural branch prediction. | Rene St. Amant, Daniel A. Jimnez, Doug Burger |
| 2008 | Implementing high availability memory with a duplication cache. | Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan |
| 2007 | A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. | Jason Zebchuk, Elham Safi, Andreas Moshovos |
| 2007 | The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. | Thomas Y. Yeh, Petros Faloutsos, Milos D. Ercegovac, Sanjay J. Patel, Glenn Reinman |
| 2007 | Optimal versus Heuristic Global Code Scheduling. | Sebastian Winkel |
| 2007 | A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. | William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe |
| 2007 | Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. | Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas |
| 2007 | Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. | Karin Strauss, Xiaowei Shen, Josep Torrellas |
| 2007 | Implementing Signatures for Transactional Memory. | Daniel Snchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam |
| 2007 | Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. | Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin |
| 2007 | Emulating Optimal Replacement with a Shepherd Cache. | Kaushik Rajan, Ramaswamy Govindarajan |
| 2007 | Global Multi-Threaded Instruction Scheduling. | Guilherme Ottoni, David I. August |
| 2007 | Time Interpolation: So Many Metrics, So Few Registers. | Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan |
| 2007 | Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. | Onur Mutlu, Thomas Moscibroda |
| 2007 | Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. | Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi |
| 2007 | Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. | Francisco J. Mesa-Martinez, Jose Renau |
| 2007 | Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. | Albert Meixner, Michael E. Bauer, Daniel J. Sorin |
| 2007 | Leveraging 3D Technology for Improved Reliability. | Niti Madan, Rajeev Balasubramonian |
| 2007 | Process Variation Tolerant 3T1D-Based Cache Architectures. | Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks |