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International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer.Livio Soares, David K. Tam, Michael Stumm
2008Power to the people: Leveraging human physiological traits to control microprocessor frequency.Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick
2008Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins.David E. Shaw
2008Verification of chip multiprocessor memory systems using a relaxed scoreboard.Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz
2008EVAL: Utilizing processors with variation-induced timing errors.Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas
2008Efficient unicast and multicast support for CMPs.Samuel Rodrigo, Jos Flich, Jos Duato, Mark Hummel
2008Strategies for mapping dataflow blocks to distributed hardware.Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley
2008Dependence-aware transactional memory for increased concurrency.Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel
2008Token tenure: PATCHing token counting using directory-based cache coherence.Arun Raghavan, Colin Blundell, Milo M. K. Martin
2008Microarchitecture in the system-level integration era.Charles R. Moore
2008Tradeoffs in designing accelerator architectures for visual computing.Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel
2008Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger
2008Prefetch-Aware DRAM Controllers.Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt
2008CPR: Composable performance regression for scalable multiprocessor models.Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks
2008Token flow control.Amit Kumar, Li-Shiuan Peh, Niraj K. Jha
2008Adaptive data compression for high-performance low-power on-chip networks.Yuho Jin, Ki Hwan Yum, Eun Jung Kim
2008Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence.Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti
2008The StageNet fabric for constructing resilient multicore systems.Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke
2008Testudo: Heavyweight security analysis via statistical sampling.Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie
2008Toward a multicore architecture for real-time ray-tracing.Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary K. Vernon, William R. Mark
2008A distributed processor state management architecture for large-window processors.Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramrez, Adrin Cristal, Mateo Valero
2008A performance-correctness explicitly-decoupled architecture.Alok Garg, Michael C. Huang
2008NBTI tolerant microarchitecture design in the presence of process variation.Xin Fu, Tao Li, Jos A. B. Fortes
2008Temporal instruction fetch streaming.Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos
2008Reconfigurable energy efficient near threshold cache architectures.Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztin Flautner
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