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International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.Boris Grot, Stephen W. Keckler, Onur Mutlu
2009Coordinated control of multiple prefetchers in multi-core systems.Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt
2009Portable compiler optimisation across embedded programs and microarchitectures using machine learning.Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle
2009Application-aware prioritization mechanisms for on-chip networks.Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
2009Yield enhancement by robust application-specific mapping on Network-on-Chips.A. Dutta Choudhury, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
2009Path-based, randomized, oblivious, minimal routing.Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel A. Kinsy, Srinivas Devadas
2009Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.Sangyeun Cho, Hyunjin Lee
2009Improving cache lifetime reliability at ultra-low voltages.Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2009Control flow obfuscation with information flow tracking.Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang, Pen-Chung Yew
2009Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.Mainak Chaudhuri
2009Characterizing the resource-sharing levels in the UltraSPARC T2 processor.Vladimir Cakarevic, Petar Radojkovic, Javier Verd, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2009Proactive transaction scheduling for contention management.Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge
2009ZerehCache: armoring cache architectures in high defect density technologies.Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke
2009BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff, David C. Wong
2009In-network coherence filtering: snoopy coherence without broadcasts.Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
2009Low Vccmin fault-tolerant cache with highly predictable performance.Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio Gonzlez
2008Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu
2008Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.Wangyuan Zhang, Tao Li
2008Notary: Hardware techniques to enhance signatures.Luke Yen, Stark C. Draper, Mark D. Hill
2008From SODA to scotch: The evolution of a wireless baseband processor.Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztin Flautner
2008A novel cache architecture with enhanced performance and security.Zhenghong Wang, Ruby B. Lee
2008SHARK: Architectural support for autonomic protection against stealth by rootkit exploits.Vikas R. Vasisht, Hsien-Hsin S. Lee
2008Facelift: Hiding and slowing down aging in multicores.Abhishek Tiwari, Josep Torrellas
2008A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood
2008Copy or Discard execution model for speculative parallelization on multicores.Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta
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