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International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches.Daniele Ludovici, Alessandro Strano, Davide Bertozzi
2009Finding concurrency bugs with context-aware communication graphs.Brandon Lucia, Luis Ceze
2009Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.Gabriel H. Loh
2009McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi
2009Offline symbolic analysis for multi-processor execution replay.Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang, Cristiano Pereira
2009Improving memory bank-level parallelism in the presence of prefetching.Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt
2009Reducing peak power with a table-driven adaptive processor core.Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar
2009Router microarchitecture and scalability of ring topology in on-chip networks.John Kim, Hanjoon Kim
2009Low-cost router microarchitecture for on-chip networks.John Kim
2009Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling.Ka-Ming Keung, Akhilesh Tyagi
2009A microarchitecture-based framework for pre- and post-silicon power delivery analysis.Mahesh Ketkar, Eli Chiprout
2009The BubbleWrap many-core: popping cores for sequential acceleration.Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
2009Ordering decoupled metadata accesses in multiprocessors.Hari Kannan
2009Optimizing shared cache behavior of chip multiprocessors.Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk
2009DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage.Changhee Jung, Nathan Clark
2009ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem.Ciji Isen, Lizy Kurian John
2009Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems.Kelli Ireland, Joseph Jezak, Steven P. Levitan, Donald M. Chiarulli
2009Why design must change: rethinking digital design.Mark Horowitz
2009SCARAB: a single cycle adaptive routing and bufferless network.Mitchell Hayenga, Natalie D. Enright Jerger, Mikko H. Lipasti
2009mSWAT: low-cost hardware fault detection and diagnosis for multicore systems.Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve
2009Segment gating for static energy reduction in Networks-on-Chip.Kyle C. Hale, Boris Grot, Stephen W. Keckler
2009Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel
2009Tribeca: design for PVT variations with local recovery and fine-grained adaptation.Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks
2009System-level exploration of run-time clusterization for energy-efficient on-chip communication.Liang Guang, Ethiopia Nigussie, Hannu Tenhunen
2009Characterizing flash memory: anomalies, observations, and applications.Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, Jack K. Wolf
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