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International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009A tagless coherence directory.Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos
2009Complexity effective memory access scheduling for many-core accelerator architectures.George L. Yuan, Ali Bakhoda, Tor M. Aamodt
2009The era of many-modules SoC: revisiting the NoC mapping problem.Isask'har Walter, Israel Cidon, Avinoam Kolodny, Daniel Sigalov
2009A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors.Jess Camacho Villanueva, Jos Flich, Jos Duato, Hans Eberle, Nils Gura, Wladek Olesinski
2009Light speed arbitration and flow control for nanophotonic interconnects.Dana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti
2009An hybrid eDRAM/SRAM macrocell to implement first-level data caches.Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro Lpez, Jos Duato
2009EazyHTM: eager-lazy hardware transactional memory.Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adri Armejach, Adrin Cristal, Osman S. Unsal, Tim Harris, Mateo Valero
2009Execution leases: a hardware-supported mechanism for enforcing strong non-interference.Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood
2009Wire cost and communication analysis of self-assembled interconnect models for Networks-on-Chip.Christof Teuscher, Neha Parashar, Mrugesh Mote, Nolan Hergert, Jonathan Aherne
2009SHARP control: controlled shared cache management in chip multiprocessors.Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang
2009Using a configurable processor generator for computer architecture prototyping.Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz
2009POWER7 multi-core processor design.Balaram Sinharoy
2009Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures.Alex Shye, Benjamin Scholbrock, Gokhan Memik
2009Multiple clock and voltage domains for chip multi processors.Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser
2009Tree register allocation.Hongbo Rong
2009Adaptive line placement with theDyer Roln, Basilio B. Fraguela, Ramon Doallo
2009Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, Blent Abali
2009Architecting a chunk-based memory race recorder in modern CMPs.Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai
2009Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications.Hyunchul Park, Yongjun Park, Scott A. Mahlke
2009Hybrid wireless Network on Chip: a new paradigm in multi-core design.Partha Pratim Pande, Amlan Ganguly, Kevin Chang, Christof Teuscher
2009Light64: lightweight hardware support for data race detection during systematic testing of parallel programs.Adrian Nistor, Darko Marinov, Josep Torrellas
2009A case for dynamic frequency tuning in on-chip networks.Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2009Adaptive router architecture based on traffic behavior observability.Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Mrcio Eduardo Kreutz
2009Toward a science for future NoC design.Radu Marculescu
2009Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping.Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim
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