| 2003 | Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches. | Se-Hyun Yang, Babak Falsafi |
| 2003 | Power-driven Design of Router Microarchitectures in On-chip Networks. | Hangsheng Wang, Li-Shiuan Peh, Sharad Malik |
| 2003 | WaveScalar. | Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin |
| 2003 | Efficient Memory Integrity Verification and Encryption for Secure Processors. | G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas |
| 2003 | Scalable Hardware Memory Disambiguation for High ILP Processors. | Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler |
| 2003 | In Memory of Bob Rau. | Michael S. Schlansker |
| 2003 | Universal Mechanisms for Data-Parallel Architectures. | Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger |
| 2003 | Reducing Design Complexity of the Load/Store Queue. | Il Park, Chong-liang Ooi, T. N. Vijaykumar |
| 2003 | A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin |
| 2003 | The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. | Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen |
| 2003 | VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. | Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy |
| 2003 | Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. | Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen |
| 2003 | Hardware Support for Control Transfers in Code Caches. | Ho-Seop Kim, James E. Smith |
| 2003 | Macro-op Scheduling: Relaxing Scheduling Loop Constraints. | Ilhyun Kim, Mikko H. Lipasti |
| 2003 | IPStash: a Power-Efficient Memory Architecture for IP-lookup. | Stefanos Kaxiras, Georgios Keramidas |
| 2003 | Fast Path-Based Neural Branch Prediction. | Daniel A. Jimnez |
| 2003 | Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data. | Canturk Isci, Margaret Martonosi |
| 2003 | Generational Cache Management of Code Traces in Dynamic Optimization Systems. | Kim M. Hazelwood, Michael D. Smith |
| 2003 | Optimum Power/Performance Pipeline Depth. | Allan Hartstein, Thomas R. Puzak |
| 2003 | Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. | Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen |
| 2003 | Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. | Enric Gibert, F. Jess Snchez, Antonio Gonzlez |
| 2003 | Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. | Jorge Garca-Vidal, Jess Corbal, Lloren Cerd, Mateo Valero |
| 2003 | Using Interaction Costs for Microarchitectural Bottleneck Analysis. | Brian A. Fields, Rastislav Bodk, Mark D. Hill, Chris J. Newburn |
| 2003 | Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. | Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztin Flautner, Trevor N. Mudge |
| 2003 | Comparing Program Phase Detection Techniques. | Ashutosh S. Dhodapkar, James E. Smith |