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International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2003Processor Acceleration Through Automated Instruction Set Customization.Nathan Clark, Hongtao Zhong, Scott A. Mahlke
2003The Reconfigurable Streaming Vector Processor (RSVPTM).Silviu M. S. A. Chiricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael A. Schuette, Ali Saidi
2003Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
2003Microarchitecture on the MOSFET Diet.Kerry Bernstein
2003TLC: Transmission Line Caches.Bradford M. Beckmann, David A. Wood
2003Beating in-order stalls with "flea-flicker" two-pass pipelining.Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu
2003IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems.Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach
2003Exploiting Value Locality in Physical Register Files.Saisanthosh Balakrishnan, Gurindar S. Sohi
2003Instruction Replication for Clustered Microarchitectures.Alex Alet, Josep M. Codina, Antonio Gonzlez, David R. Kaeli
2003Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors.Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
2003LLVA: A Low-level Virtual Instruction Set Architecture.Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke
2002Master/slave speculative parallelization.Craig B. Zilles, Gurindar S. Sohi
2002Compiler-directed instruction cache leakage optimization.Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2002Energy efficient frequent value data cache design.Jun Yang, Rajiv Gupta
2002Compiler managed micro-cache bypassing for high performance EPIC processors.Youfeng Wu, Ryan N. Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang
2002Orion: a power-performance simulator for interconnection networks.Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik
2002Microarchitectural exploration with Liberty.Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, David I. August
2002Using modern graphics architectures for general-purpose computing: a framework and analysis.Chris J. Thompson, Sahngyun Hahn, Mark Oskin
2002Optimizing pipelines for power and performance.Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
2002Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.Andr Seznec, Eric Toullec, Olivier Rochecouste
2002Dynamic frequency and voltage control for a multiple clock domain microarchitecture.Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott
2002A quantitative framework for automated pre-execution thread selection.Amir Roth, Gurindar S. Sohi
2002Fetching instruction streams.Alex Ramrez, Oliverio J. Santana, Josep Llus Larriba-Pey, Mateo Valero
2002Three extensions to register integration.Vlad Petric, Anne Bracy, Amir Roth
2002Reducing register ports for higher speed and lower energy.Il Park, Michael D. Powell, T. N. Vijaykumar
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