| 2001 | Select-free instruction scheduling logic. | Mary D. Brown, Jared Stark, Yale N. Patt |
| 2001 | Reducing the complexity of the register file in dynamic superscalar processors. | Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi |
| 2001 | Graph-partitioning based instruction scheduling for clustered processors. | Alex Alet, Josep M. Codina, F. Jess Snchez, Antonio Gonzlez |
| 2000 | A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. | Zhao Zhang, Zhichun Zhu, Xiaodong Zhang |
| 2000 | Two-level hierarchical register file organization for VLIW processors. | Javier Zalamea, Josep Llosa, Eduard Ayguad, Mateo Valero |
| 2000 | Frequent value compression in data caches. | Jun Yang, Youtao Zhang, Rajiv Gupta |
| 2000 | Improving BTB performance in the presence of DLLs. | Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson |
| 2000 | Dynamic zero compression for cache energy reduction. | Luis Villa, Michael Zhang, Krste Asanovic |
| 2000 | Flexible hardware acceleration for multimedia oriented microprocessors. | Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man |
| 2000 | On pipelining dynamic instruction scheduling logic. | Jared Stark, Mary D. Brown, Yale N. Patt |
| 2000 | Accurate and efficient predicate analysis with binary decision diagrams. | John W. Sias, Wen-mei W. Hwu, David I. August |
| 2000 | Predictor-directed stream buffers. | Timothy Sherwood, Suleyman Sair, Brad Calder |
| 2000 | Modulo scheduling for a fully-distributed clustered VLIW architecture. | F. Jess Snchez, Antonio Gonzlez |
| 2000 | Register integration: a simple and efficient implementation of squash reuse. | Amir Roth, Gurindar S. Sohi |
| 2000 | A study of slipstream processors. | Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg |
| 2000 | The store-load address table and speculative register promotion. | Matt Postiff, David A. Greene, Trevor N. Mudge |
| 2000 | Increasing the size of atomic instruction blocks using control flow assertions. | Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum |
| 2000 | Reducing wire delay penalty through value prediction. | Joan-Manuel Parcerisa, Antonio Gonzlez |
| 2000 | Calpa: a tool for automating selective dynamic compilation. | Markus Mock, Craig Chambers, Susan J. Eggers |
| 2000 | Performance improvement with circuit-level speculation. | Tong Liu, Shih-Lien Lu |
| 2000 | Silent stores for free. | Kevin M. Lepak, Mikko H. Lipasti |
| 2000 | Eager writeback - a technique for improving bandwidth utilization. | Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens |
| 2000 | Compiler controlled value prediction using branch predictor based confidence. | Eric Larson, Todd M. Austin |
| 2000 | Defect tolerant molecular electronics: algorithms, architectures, and atoms. | Phil Keukes |
| 2000 | Efficient conditional operations for data-parallel architectures. | Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany |