| 1999 | Value Prediction for Speculative Multithreaded Architectures. | Pedro Marcuello, Jordi Tubella, Antonio Gonzlez |
| 1999 | Evaluation of a High Performance Code Compression Method. | Charles Lefurgy, Eva Piccininni, Trevor N. Mudge |
| 1999 | Low-Cost Branch Folding for Embedded Applications with Small Tight Loops. | Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends |
| 1999 | Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. | Sergei Y. Larin, Thomas M. Conte |
| 1999 | Instruction Fetch Mechanisms for Multipath Execution Processors. | Artur Klauser, Dirk Grunwald |
| 1999 | Improving Branch Predictors by Correlating on Data Values. | Timothy H. Heil, Zak Smith, James E. Smith |
| 1999 | Balance Scheduling: Weighting Branch Tradeoffs in Superblocks. | Alexandre E. Eichenberger, Waleed Meleis |
| 1999 | Optimizations and Oracle Parallelism with Dynamic Translation. | Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind |
| 1999 | Exploiting a New Level of DLP in Multimedia Applications. | Jess Corbal, Roger Espasa, Mateo Valero |
| 1999 | Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. | Daniel A. Connors, Wen-mei W. Hwu |
| 1999 | Hardware Identification of Cache Conflict Misses. | Jamison D. Collins, Dean M. Tullsen |
| 1999 | Access Region Locality for High-Bandwidth Processor Memory System Design. | Sangyeun Cho, Pen-Chung Yew, Gyungho Lee |
| 1999 | Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. | Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey |
| 1999 | DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. | Todd M. Austin |
| 1999 | Selective Cache Ways: On-Demand Cache Resource Allocation. | David H. Albonesi |
| 1999 | Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems. | Santosh G. Abraham, Scott A. Mahlke |
| 1998 | Better Global Scheduling Using Path Profiles. | Cliff Young, Michael D. Smith |
| 1998 | Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. | Chia-Lin Yang, Barton Sano, Alvin R. Lebeck |
| 1998 | Task Selection for a Multiscalar Processor. | T. N. Vijaykumar, Gurindar S. Sohi |
| 1998 | Load Latency Tolerance in Dynamically Scheduled Processors. | Srikanth T. Srinivasan, Alvin R. Lebeck |
| 1998 | Understanding the Differences Between Value Prediction and Instruction Reuse. | Avinash Sodani, Gurindar S. Sohi |
| 1998 | Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms. | Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark |
| 1998 | Split-path Enhanced Pipeline Scheduling for Loops with Control Flows. | SangMin Shim, Soo-Mook Moon |
| 1998 | Improving I/O Performance with a Conditional Store Buffer. | Lambert Schaelicke, Al Davis |
| 1998 | A Bandwidth-efficient Architecture for Media Processing. | Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo Lpez-Lagunas, Peter R. Mattson, John D. Owens |