| 2025 | Low-Power and Superior Performance Design of Ternary Logic Cells Using CNFET and MOSFET Devices for VLSI Applications. | Siva Chinmai Varma Bhupathiraju, Sridhara Sai Krishna, Yashwanth Komuravelly, Ramakant Yadav |
| 2025 | LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models. | Sutirtha Bhattacharyya, Fedrick Nongpoh, Karthik Maddala, E. Bhawani Eswar Reddy, Chandan Karfa |
| 2025 | MERGERS: Multi-Access Edge Resource Governance for Real-Time SaaS Systems. | Aakashjit Bhattacharya, Arnab Sarkar, Ansuman Banerjee |
| 2025 | Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design. | D. V. Bhargav, G. Pradyumna, Madhav Rao |
| 2025 | Early Bug Detector - A Verification Methodology for DFD-SoC RTL Parameters. | C. Bhagyalakshmi, Madhav Lekkala, Maneesh Pandey |
| 2025 | Effective Memory Management and Sparse Aware Cache for Row-Wise Sparse CNNs. | MC Balasubramaniam, Basava Naga Girish Koneru, Nitin Chandrachoodan |
| 2025 | Pin Efficient Tri-Level Based Inductive Coupling Transceiver for 3D ICs. | Soumojit Bakshi, V. K. Surya, Nijwm Wary |
| 2025 | An Experimental Demonstration of Neuronal Somatic Behavior Using 2D SnS Memristive Switching Characteristics and its Equivalent Circuit for Spiking Neural Network. | Anshul Awasthi, Soumi Saha, Parikshit Sahatiya, Surya Shankar Dan |
| 2025 | Optimizing Bandwidth Utilization Through Word Based Compression in Main Memories. | N. S. Aswathy, Harsh Verma, Hemangee K. Kapoor |
| 2025 | Analysis and Design Considerations for MASH of Noise Shaped SAR ADCs. | R. Arundeepakvel, Ankesh Jain |
| 2025 | A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator. | Aya G. Amer, Maitreyi Ashok, Xin Zhang, John Cohn, Anantha P. Chandrakasan |
| 2025 | AI-Driven Anomaly Detection in Oscilloscope Images for Post-Silicon Validation. | Kowshic A. Akash, Tobias Wulf, Torsten Valentin, Alexander Geist, Ulf Kulau, Sohan Lal |
| 2025 | A Fully Autonomous 1.2A Auxiliary Buck DC-DC Converter for Fast Transient Load-on-Demand. | Shivam Agarwal, Sivasai Guddanti, Qadeer A. Khan |
| 2025 | Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion. | Soham Adhikary, Ayan Palchaudhuri |
| 2025 | FARAD: Automated Formal Verification of Approximate Restoring Array Dividers. | Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan, Rolf Drechsler |
| 2025 | Low Form-Factor Switchless Dual-Band Matching Network for RF Power Harvesting Systems. | Arun Mohan, Saroj Mondal, Yash N. Rayudu, Roy P. Paily |
| 2024 | Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits. | Zainubia, Bipul Kumar Singh, Manish Pundir, Subhash Chander Dubey, Ambika Prasad Shah |
| 2024 | SMT-based Control Safety Property Checking in Cyber-Physical Systems under Timing Uncertainties. | Anand Yeolekar, Ravindra Metta, Samarjit Chakraborty |
| 2024 | Certifiable and Efficient Autonomous Cyber-Physical Systems Design. | Shengjie Xu, Clara Hobbs, Bineet Ghosh, Parasara Sridhar Duggirala, Samarjit Chakraborty |
| 2024 | DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications. | Vinod Viswanath, Kanad Chakraborty |
| 2024 | A 1.6 - 2.5 GHz Receiver for Software Defined Radio with High Linearity Mode. | Gopikrishna Vijayakumar, Alok Joshi, Abhishek Kumar |
| 2024 | A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter. | Anshul Verma, Bishnu Prasad Das |
| 2024 | Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management. | Swathi Kumar Vembu, Anupam Chattopadhyay, Sayandeep Saha |
| 2024 | Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode. | Kanupriya Varshney, Mani Shankar Yadav, Devarshi Mrinal Das, Brajesh Rawat |
| 2024 | Designing Hash and Encryption Engines using Quantum Computing. | Suryansh Upadhyay, Rupshali Roy, Swaroop Ghosh |