Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths.
Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian
Browse the full VLSID paper archive.
Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian
Browse the full VLSID paper archive.