| 2026 | ETS | Gremlins in the Silicon: Why Faulty Chips are Escaping the Fab and Crashing in the Field. | Mottaqiallah Taouil, R. D. Shawn Blanton, Phil Nigh, Adit D. Singh, Said Hamdioui |
| 2025 | DAC | Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations. | Adit D. Singh, Mukarram Ali Faridi |
| 2025 | ITC | Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance. | Gowsika Dharmaraj, Abhijit Chatterjee, Adit D. Singh, Arani Sinha |
| 2025 | VTS | Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation Strategies. | Peter Domanski, Mukarram Ali Faridi, Gabriel Kaunang, Wilson Pradeep, Adit D. Singh, Muhammad Alfian Amrizal, Yanjing Li, Farshad Firouzi, Krishnendu Chakrabarty |
| 2024 | ETS | Silent Data Corruption from Timing Marginalities Due to Process Variations. | Adit D. Singh |
| 2024 | VTS | Innovative Practices Track: Session 2 Silent Data Corruption. | Arani Sinha, Adit D. Singh |
| 2023 | VTS | Silent Data Errors: Sources, Detection, and Modeling. | Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos |
| 2022 | ITC | Understanding Vmin Failures for Improved Testing of Timing Marginalities. | Adit D. Singh |
| 2021 | VTS | Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
| 2020 | ITC | SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
| 2020 | VTS | A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture. | Wendong Wang, Ujjwal Guin, Adit D. Singh |
| 2019 | ITC | An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures. | Adit D. Singh |
| 2019 | VLSID | Two-Pattern ∆IDDQ Test for Recycled IC Detection. | Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal |
| 2018 | ETS | Device aging: A reliability and security concern. | Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi |
| 2018 | VLSID | A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. | Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum |
| 2017 | DATE | Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. | Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker |
| 2017 | ETS | Best paper. | Bernd Becker, Adit D. Singh |
| 2017 | ITC | Exploiting path delay test generation to develop better TDF tests for small delay defects. | Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja |
| 2017 | VTS | Efficient SAT-based generation of hazard-activated TSOF tests. | Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker |
| 2017 | VTS | A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. | Ujjwal Guin, Ziqi Zhou, Adit D. Singh |
| 2016 | ETS | Cell Aware and stuck-open tests. | Adit D. Singh |
| 2016 | VLSID | Adaptive Test Methods for High IC Quality and Reliability. | Adit D. Singh |
| 2015 | VLSID | Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. | Adit D. Singh |
| 2015 | VLSID | An Efficient Transition Detector Exploiting Charge Sharing. | Yu Wang, Adit D. Singh |
| 2015 | VTS | Special session: Hot topics: Statistical test methods. | Manuel J. Barragn, Gildas Lger, Florence Azas, Ronald D. Blanton, Adit D. Singh, Stephen Sunter |
| 2015 | VTS | Testing cross wire opens within complex gates. | Chao Han, Adit D. Singh |
| 2014 | ETS | Detection conditions for errors in self-adaptive better-than-worst-case designs. | Ilia Polian, Jie Jiang, Adit D. Singh |
| 2014 | ETS | Error detection and recovery in better-than-worst-case timing designs. | Adit D. Singh |
| 2014 | ITC | On the testing of hazard activated open defects. | Chao Han, Adit D. Singh |
| 2014 | VLSID | Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. | Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh |
| 2014 | VLSID | Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. | Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian |
| 2014 | VTS | Improving CMOS open defect coverage using hazard activated tests. | Chao Han, Adit D. Singh |
| 2013 | ETS | Current testing: Dead or alive? | Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello |
| 2013 | VLSID | A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. | Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee |
| 2013 | VTS | Special session 4B: Elevator talks. | Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia |
| 2012 | IOLTS | SEU tolerant robust memory cell design. | Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita |
| 2012 | VTS | Detection of gate-oxide defects with timing tests at reduced power supply. | Xi Qian, Chao Han, Adit D. Singh |
| 2011 | VLSID | Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. | Kautalya Mishra, Ahmed Faraz, Adit D. Singh |
| 2010 | DATE | Adapting to adaptive testing. | Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli |
| 2010 | ETS | Modified T-Flip-Flop based scan cell for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
| 2010 | ISCAS | Test application time minimization for RAS using basis optimization of column decoder. | A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
| 2010 | VLSID | On Minimization of Test Application Time for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
| 2010 | VTS | An output compression scheme for handling X-states from over-clocked delay tests. | Adit D. Singh, Chao Han, Xi Qian |
| 2009 | IOLTS | Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. | Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou |
| 2009 | VTS | Output Hazard-Free Transition Delay Fault Test Generation. | Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal |
| 2008 | ITC | Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. | Adit D. Singh |
| 2008 | VLSID | Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. | Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee |
| 2008 | VLSID | Scan Delay Testing of Nanometer SoCs. | Adit D. Singh |
| 2007 | ITC | Achieving high transition delay fault coverage with partial DTSFF scan chains. | Gefu Xu, Adit D. Singh |
| 2007 | VLSID | Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. | Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril |
| 2007 | VLSID | Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. | Gefu Xu, Adit D. Singh |
| 2006 | ETS | Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. | Gefu Xu, Adit D. Singh |
| 2006 | VLSID | Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak |
| 2006 | VTS | Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. | Adit D. Singh, Gefu Xu |
| 2005 | ASPDAC | Low-power domino circuits using NMOS pull-up on off-critical paths. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2005 | ICCD | A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De |
| 2005 | ITC | A random access scans architecture to reduce hardware overhead. | Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh |
| 2005 | ITC | A self-timed structural test methodology for timing anomalies due to defects and process variations. | Adit D. Singh |
| 2005 | VLSID | Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2005 | VLSID | A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. | Haihua Yan, Adit D. Singh |
| 2005 | VTS | Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2004 | ETS | Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. | Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh |
| 2004 | IOLTS | Sizing CMOS Circuits for Increased Transient Error Tolerance. | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh |
| 2004 | ITC | Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. | Haihua Yan, Adit D. Singh |
| 2003 | ITC | Relating Yield Models to Burn-In Fall-Out in Time. | Thomas S. Barnett, Adit D. Singh |
| 2003 | ITC | Should Nanometer Circuits be Periodically Tested in the Field? | Adit D. Singh |
| 2003 | ITC | Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. | Haihua Yan, Adit D. Singh |
| 2002 | ITC | Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. | Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh |
| 2002 | VTS | Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. | Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy |
| 2002 | VTS | Scan-Path with Directly Duplicated and Inverted Duplicated Registers. | Michael Gssel, Egor S. Sogomonyan, Adit D. Singh |
| 2001 | ITC | Estimating burn-in fall-out for redundant memory. | Thomas S. Barnett, Adit D. Singh, Victor P. Nelson |
| 2001 | VTS | Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. | Thomas S. Barnett, Adit D. Singh, Victor P. Nelson |
| 2001 | VTS | Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. | Egor S. Sogomonyan, Andrej A. Morosov, Jan Rzeha, Michael Gssel, Adit D. Singh |
| 1999 | ITC | Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. | David R. Lakin II, Adit D. Singh |
| 1999 | ITC | Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. | Adit D. Singh, Egor S. Sogomonyan, Michael Gssel, Markus Seuring |
| 1998 | VTS | A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. | Egor S. Sogomonyan, Adit D. Singh, Michael Gssel |
| 1997 | ITC | Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. | Adit D. Singh, Phil Nigh, C. Mani Krishna |
| 1995 | ITC | I | Adit D. Singh, Haroon Rasheed, Walter W. Weber |
| 1995 | VLSID | A differential built-in current sensor design for high speed IDDQ testing. | Jason P. Hurst, Adit D. Singh |
| 1995 | VTS | An experimental evaluation of the differential BICS for I | Walter W. Weber, Adit D. Singh |
| 1994 | VTS | Incorporating IDDQ testing in BIST: improved coverage through test diversity. | Adit D. Singh, Jason P. Hurst |
| 1993 | VTS | The effect of defect clustering on test transparency and defect levels. | Adit D. Singh, C. Mani Krishna |
| 1992 | VTS | Analysis of the die test optimization algorithm for negative binomial yield statistics. | C. Mani Krishna, Adit D. Singh |
| 1991 | ITC | On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. | Adit D. Singh, C. Mani Krishna |
| 1989 | ICCAD | An efficient channel routing algorithm for defective arrays. | Hee Yong Youn, Adit D. Singh |
| 1989 | ICPP | A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. | Hee Yong Youn, Adit D. Singh |
| 1988 | ICDCS | Near Optimal Embedding of Binary Tree Architecture in VLSI. | Hee Yong Youn, Adit D. Singh |
| 1988 | ICPP | A Highly Efficient Design for Reconfiguring the Processor Array in VLSI. | Hee Yong Youn, Adit D. Singh |
| 1987 | ICPP | On Area Efficient and Fault Tolerant Tree Embedding In VLSI. | Hee Yong Youn, Adit D. Singh |