Alan Mishchenko
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
104
Venues
19
Active years
1999–2025
Best venue rank
A*
Where they publish
Papers
104 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | Area-Oriented Optimization After Standard-Cell Mapping. | Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli |
| 2025 | ASPDAC | High-Effort Logic Synthesis Using Randomized Transduction. | Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruic, Xiaoqing Xu |
| 2025 | DATE | SimGen: Simulation Pattern Generation for Efficient Equivalence Checking. | Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic |
| 2025 | ICCAD | Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization. | Jiun-Hao Chen, Jie-Hong R. Jiang, Alan Mishchenko |
| 2025 | VLSID | Symmetry-Based Synthesis for Interpretable Boolean Evaluation. | Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli |
| 2024 | DATE | Scalable Sequential Optimization Under Observability Don't Cares. | Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amar |
| 2024 | FCCM | Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. | Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser |
| 2024 | ISCAS | An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization. | Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli |
| 2024 | UC | High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. | Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury |
| 2023 | DAC | Improving Standard-Cell Design Flow using Factored Form Optimization. | Alessandro Tempia Calvino, Alan Mishchenko, Herman Schmit, Ethan Mahintorabi, Giovanni De Micheli, Xiaoqing Xu |
| 2023 | DATE | Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. | Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek |
| 2023 | ICCAD | Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. | Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu |
| 2022 | ASPDAC | Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. | Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli |
| 2022 | DAC | Improving LUT-based optimization for ASICs. | Walter Lau Neto, Luca G. Amar, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon |
| 2021 | DAC | LUT-Based Optimization For ASIC Design Flow. | Luca Gaetano Amar, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2021 | DAC | Deep Integration of Circuit Simulator and SAT Solver. | He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amar, Alan Mishchenko, Robert K. Brayton |
| 2021 | DATE | Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. | Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jnata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee |
| 2021 | ICCAD | A Circuit-Based SAT Solver for Logic Synthesis. | He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko |
| 2020 | DAC | SAT-Sweeping Enhanced for Logic Synthesis. | Luca G. Amar, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2020 | DAC | ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set. | Chang Meng, Weikang Qian, Alan Mishchenko |
| 2020 | DATE | Exact DAG-Aware Rewriting. | Heinz Riener, Alan Mishchenko, Mathias Soeken |
| 2020 | ICML | Circuit-Based Intrinsic Methods to Detect Overfitting. | Satrajit Chatterjee, Alan Mishchenko |
| 2019 | DAC | Scalable Generic Logic Synthesis: One Approach to Rule Them All. | Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amar, Giovanni De Micheli, Mathias Soeken |
| 2019 | DATE | On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. | Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken |
| 2019 | DATE | Scalable Boolean Methods in a Modern Synthesis Flow. | Eleonora Testa, Luca G. Amar, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2018 | ASPDAC | SAT-based area recovery in structural technology mapping. | Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton |
| 2018 | DAC | Efficient computation of ECO patch functions. | Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton |
| 2018 | DAC | SAT based exact synthesis using DAG topology families. | Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli |
| 2018 | DAC | Canonical computation without canonical representation. | Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amar, Antun Domic |
| 2018 | DATE | Improvements to boolean resynthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2018 | DATE | Practical exact synthesis. | Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amar, Robert K. Brayton, Giovanni De Micheli |
| 2018 | FPGA | Improving FPGA Performance with a S44 LUT Structure. | Wenyi Feng, Jonathan W. Greene, Alan Mishchenko |
| 2018 | FPL | Fast Adjustable NPN Classification using Generalized Symmetries. | Xuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko |
| 2018 | ICCAD | Unlocking fine-grain parallelism for AIG rewriting. | Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, Andr Incio Reis |
| 2018 | LPAR | Rewriting Environment for Arithmetic Circuit Verification. | Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski |
| 2017 | ASPDAC | Fast-extract with cube hashing. | Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, Andr Incio Reis |
| 2017 | DATE | Busy man's synthesis: Combinational delay optimization with SAT. | Mathias Soeken, Giovanni De Micheli, Alan Mishchenko |
| 2017 | FMCAD | Property directed reachability with word-level abstraction. | Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton |
| 2017 | ICCAD | Enabling exact delay synthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2016 | AAAI | Clauses Versus Gates in CEGAR-Based 2QBF Solving. | Valeriy Balabanov, Jie-Hong Roland Jiang, Alan Mishchenko, Christoph Scholl |
| 2016 | FMCAD | Efficient uninterpreted function abstraction and refinement for word-level model checking. | Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton |
| 2016 | FPL | Fast hierarchical NPN classification. | Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko |
| 2016 | ICCAD | Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. | Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne |
| 2016 | SAT | 2QBF: Challenges and Solutions. | Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton |
| 2016 | SAT | Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. | Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli |
| 2015 | FPGA | Technology Mapping into General Programmable Cells. | Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene |
| 2015 | ICCAD | Threshold Logic Synthesis Based on Cut Pruning. | Augusto Neutzling, Jody Maick Matos, Andr Incio Reis, Renato P. Ribas, Alan Mishchenko |
| 2015 | SEFM | Automated Synthesis of Protocol Converters with BALM-II. | Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko |
| 2014 | ASPDAC | ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. | Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury |
| 2014 | ICCAD | Constrained interpolation for guided logic synthesis. | Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne |
| 2014 | ITC | Efficient SAT-based ATPG techniques for all multiple stuck-at faults. | Masahiro Fujita, Alan Mishchenko |
| 2013 | DATE | Core minimization in SAT-based abstraction. | Anton Belov, Huan Chen, Alan Mishchenko, Joo Marques-Silva |
| 2013 | DATE | GLA: gate-level abstraction revisited. | Alan Mishchenko, Niklas En, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla |
| 2013 | DATE | A semi-canonical form for sequential AIGs. | Alan Mishchenko, Niklas En, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma |
| 2013 | FMCAD | A Fast Reparameterization Procedure. | Niklas En, Alan Mishchenko |
| 2013 | FMCAD | Trading-off Incrementality and Dynamic Restart of Multiple Solvers in IC3. | Marco Palena, Gianpiero Cabodi, Alan Mishchenko |
| 2012 | DATE | Mapping into LUT structures. | Sayak Ray, Alan Mishchenko, Niklas En, Robert K. Brayton, Stephen Jang, Chao Chen |
| 2012 | ICCAD | Lazy man's logic synthesis. | Wenlong Yang, Lingli Wang, Alan Mishchenko |
| 2011 | FMCAD | Efficient implementation of property directed reachability. | Niklas En, Alan Mishchenko, Robert K. Brayton |
| 2011 | FMCAD | Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. | Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton |
| 2011 | ICCAD | Delay optimization using SOP balancing. | Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets |
| 2010 | CAV | ABC: An Academic Industrial-Strength Verification Tool. | Robert K. Brayton, Alan Mishchenko |
| 2010 | DATE | Monolithically stackable hybrid FPGA. | Dmitri B. Strukov, Alan Mishchenko |
| 2010 | FMCAD | A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. | Niklas En, Alan Mishchenko, Nina Amla |
| 2010 | FMCAD | Combinational techniques for sequential equivalence checking. | Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton |
| 2010 | FPGA | Global delay optimization using structural choices. | Alan Mishchenko, Robert K. Brayton, Stephen Jang |
| 2010 | FPL | Efficient FPGA Resynthesis Using Precomputed LUT Structures. | Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu |
| 2009 | DATE | Sequential logic synthesis using symbolic bi-decomposition. | Victor N. Kravets, Alan Mishchenko |
| 2009 | DATE | Speculative reduction-based scalable redundancy identification. | Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton |
| 2009 | FPGA | SmartOpt: an industrial strength framework for logic synthesis. | Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton |
| 2009 | FPGA | Scalable don't-care-based logic optimization and resynthesis. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang |
| 2008 | DAC | Merging nodes under sequential observability. | Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton |
| 2008 | DAC | Scalable min-register retiming under timing and initializability constraints. | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton |
| 2008 | FMCAD | Invariant-Strengthened Elimination of Dependent State Elements. | Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony |
| 2008 | FMCAD | Recording Synthesis History for Sequential Verification. | Alan Mishchenko, Robert K. Brayton |
| 2008 | FPGA | WireMap: FPGA technology mapping for improved routability. | Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko |
| 2008 | ICCAD | Boolean factoring and decomposition of logic networks. | Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee |
| 2008 | ICCAD | Scalable and scalably-verifiable sequential synthesis. | Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang |
| 2007 | DAC | On Resolution Proofs for Combinational Equivalence. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann |
| 2007 | FMCAD | Automated Extraction of Inductive Invariants to Aid Model Checking. | Michael L. Case, Alan Mishchenko, Robert K. Brayton |
| 2007 | FMCAD | Fast Minimum-Register Retiming via Binary Maximum-Flow. | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton |
| 2007 | ICCAD | Scalable exploration of functional dependency by interpolation and incremental SAT solving. | Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko |
| 2007 | ICCAD | Combinational and sequential mapping with priority cuts. | Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton |
| 2007 | SAT | Applying Logic Synthesis for Speeding Up SAT. | Niklas En, Alan Mishchenko, Niklas Srensson |
| 2006 | DAC | DAG-aware AIG rewriting a fresh look at combinational logic synthesis. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton |
| 2006 | DAC | Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. | Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske |
| 2006 | FPGA | Improvements to technology mapping for LUT-based FPGAs. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton |
| 2006 | ICCAD | Factor cuts. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton |
| 2006 | ICCAD | Improvements to combinational equivalence checking. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas En |
| 2005 | ASPDAC | Detecting support-reducing bound sets using two-cofactor symmetries. | Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch |
| 2005 | DATE | SAT-Based Complete Don't-Care Computation for Network Optimization. | Alan Mishchenko, Robert K. Brayton |
| 2005 | DATE | Efficient Solution of Language Equations Using Partitioned Representations. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko |
| 2005 | ICCAD | Reducing structural bias in technology mapping. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam |
| 2005 | ISCAS | Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. | Malgorzata Chrzanowska-Jeske, Alan Mishchenko |
| 2004 | ICCAD | On breakable cyclic definitions. | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton |
| 2003 | DAC | Large-scale SOP minimization using decomposition and functional properties. | Alan Mishchenko, Tsutomu Sasao |
| 2003 | DAC | A new enhanced constructive decomposition and mapping algorithm. | Alan Mishchenko, Xinning Wang, Timothy Kam |
| 2003 | DATE | Reducing Multi-Valued Algebraic Operations to Binary. | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton |
| 2003 | ICCAD | A Theory of Non-Deterministic Networks. | Alan Mishchenko, Robert K. Brayton |
| 2002 | ICCAD | Simplification of non-deterministic multi-valued networks. | Alan Mishchenko, Robert K. Brayton |
| 2002 | ICCAD | Topologically constrained logic synthesis. | Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton |
| 2001 | DAC | An Algorithm for Bi-Decomposition of Logic Functions. | Alan Mishchenko, Bernd Steinbach, Marek A. Perkowski |
| 2001 | DSD | Regular Realization of Symmetric Functions Using Reversible Logic. | Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Jzwiak, Alan J. Coppola |
| 1999 | DAC | Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. | Marek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko |