| 2020 | SACI | Layered LDPC decoder in-order message access scheduling: a case study. | Oana Boncalo, Alexandru Amaricai |
| 2019 | DSD | Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller. | Oana Boncalo, Alexandru Amaricai, Zsfia Lendek |
| 2018 | DSD | Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding. | Oana Boncalo, Alexandru Amaricai, Sergiu Nimara |
| 2016 | DDECS | FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization. | Sergiu Nimara, Oana Boncalo, Alexandru Amaricai, Mircea Popa |
| 2015 | DDECS | Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques. | Ioana Mot, Oana Boncalo, Alexandru Amaricai |
| 2015 | SACI | Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands. | Sergiu Nimara, Alexandru Amaricai, Mircea Popa |
| 2015 | SACI | Generation of floating point 2D translation operators for FPGA. | Ovidiu Sicoe, Alexandru Amaricai, Mircea Popa |
| 2014 | DSD | Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits. | Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici |
| 2014 | FPL | An FPGA sliding window-based architecture harris corner detector. | Alexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo |
| 2014 | FPL | Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing. | Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin |
| 2011 | SACI | Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator. | Alexandru Amaricai, Alin Dobre, Oana Boncalo, Andrei V. Tanase, Camelia Valuch |
| 2009 | DSD | Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation. | Alexandru Amaricai, Oana Boncalo |
| 2009 | DSD | Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation. | Oana Boncalo, Alexandru Amaricai |
| 2008 | DDECS | A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. | Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu |
| 2007 | DDECS | Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. | Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo |
| 2007 | DSD | Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. | Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo |
| 2007 | DSD | Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |
| 2007 | SACI | Simulated Fault Injection for Quantum Circuits Based on Simulator Commands. | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |