| 2024 | DATE | BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. | Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu |
| 2023 | ISCAS | H-RIS: Hybrid Computing-in-Memory Architecture Exploring Repetitive Input Sharing. | Yu-Chen Chen, Cheng-Yang Chang, An-Yeu Wu |
| 2021 | ISCAS | A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification. | Cheng-Lin Lee, Yi-Ta Chen, An-Yeu Wu |
| 2018 | ICASSP | Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving. | Kai-Ni Hou, Ting-Sheng Chen, Hung-Chi Kuo, Tzu-Hsuan Chen, An-Yeu Wu |
| 2017 | ICASSP | Compressive sensing based ECG monitoring with effective AF detection. | Hung-Chi Kuo, Yu-Min Lin, An-Yeu Wu |
| 2014 | ISCAS | High-throughput QC-LDPC decoder with cost-effective early termination scheme for non-volatile memory systems. | Yu-Min Lin, Yu-Hao Chen, Ming-Han Chung, An-Yeu Wu |
| 2014 | IWSEC | Hydra: An Energy-Efficient Programmable Cryptographic Coprocessor Supporting Elliptic-Curve Pairings over Fields of Large Characteristics. | Yun-An Chang, Wei-Chih Hong, Ming-Chun Hsiao, Bo-Yin Yang, An-Yeu Wu, Chen-Mou Cheng |
| 2013 | ICASSP | Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems. | Ming-Han Chung, Yu-Min Lin, Cheng-Zhou Zhan, An-Yeu Wu |
| 2009 | ASPDAC | A 52-mW 8.29mm | Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu |
| 2009 | ISCAS | A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM. | Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Wu |
| 2009 | ISCAS | A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems. | Shu-Yen Lin, Chan-Cheng Hsu, An-Yeu Wu |
| 2008 | ICASSP | High-performance scheduling algorithm for partially parallel LDPC decoder. | Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu |
| 2008 | ISCAS | Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. | Yen-Liang Chen, Cheng-Zhou Zhan, An-Yeu Wu |
| 2008 | ISCAS | Low-power traceback MAP decoding for double-binary convolutional turbo decoder. | Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu |
| 2008 | ISCAS | An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. | Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu |
| 2007 | ISCAS | A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. | Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien |
| 2007 | ISCAS | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. | Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao |
| 2007 | ISCAS | Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. | Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu |
| 2006 | ISCAS | DSP engine design for LINC wireless transmitter systems. | Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao |
| 2006 | ISCAS | A portable all-digital pulsewidth control loop for SOC applications. | Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu |
| 2006 | ISCAS | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. | Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu |
| 2005 | ICASSP | Low cost decision feedback equalizer (DFE) design for Giga-bit systems. | Chih-Hsiu Lin, An-Yeu Wu |
| 2005 | ISCAS | Digital signal processing engine design for polar transmitter in wireless communication systems. | Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu |
| 2005 | ISCAS | A memory-reduced log-MAP kernel for turbo decoder. | Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu |
| 2005 | ISCAS | A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. | I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu |
| 2005 | ISCAS | A scalable DCO design for portable ADPLL designs. | Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu |
| 2004 | ISCAS | VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. | Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu |
| 2004 | ISCAS | A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. | Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu |
| 2004 | ISCAS | 1000BASE-T Gigabit Ethernet baseband DSP IC design. | Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu |
| 2004 | ISCAS | Least squares approximation-based ROM-free direct digital frequency synthesizer. | Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu |
| 2003 | ICASSP | Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-performance rotational operations. | Zhi-Xiu Lin, An-Yeu Wu |
| 2003 | ICASSP | Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm. | An-Yeu Wu, I-Hsien Lee, Cheng-Shing Wu |
| 2003 | ISCAS | Implementation of a programmable 64~2048-point FFT/IFFT processor for OFDM-based communication systems. | Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu |
| 2002 | ISCAS | A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. | Cheng-Shing Wu, An-Yeu Wu |
| 2002 | ISCAS | A new pipelined adaptive DFE architecture with improved convergence rate. | Meng-Da Yang, An-Yeu Wu |
| 2001 | ICASSP | Cost-efficient multiplier-less FIR filter structure based on modified DECOR transformation. | I-Hsien Lee, Cheng-Shing Wu, An-Yeu Wu |
| 2001 | ICASSP | A novel trellis-based searching scheme for EEAS-based CORDIC algorithm. | Cheng-Shing Wu, An-Yeu Wu |
| 2001 | ICASSP | A unified design framework for vector rotational CORDIC family based on angle quantization process. | An-Yeu Wu, Cheng-Shing Wu |
| 2001 | ISCAS | An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. | Chi-Li Yu, An-Yeu Wu |
| 2000 | ISCAS | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem. | Jye-Jong Leu, An-Yeu Wu |
| 2000 | ISCAS | Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT. | Cheng-Shing Wu, An-Yeu Wu |
| 1999 | ICASSP | A novel multirate adaptive FIR filtering algorithm and structure. | Cheng-Shing Wu, An-Yeu Wu |
| 1998 | ICASSP | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology. | An-Yeu Wu, Tsun-Shan Chan |
| 1995 | ICASSP | Algorithm-based low-power transform coding architectures. | An-Yeu Wu, K. J. Ray Liu |
| 1995 | ICIP | Parallel programmable video co-processor design. | An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu |
| 1994 | ISCAS | A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. | An-Yeu Wu, K. J. Ray Liu |
| 1993 | ISCAS | A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation. | K. J. Ray Liu, An-Yeu Wu |