| 2024 | DDECS | An Autonomous Clock Frequency Supervision Circuit. | Clemens Scharwitzl, Andreas Steininger |
| 2024 | IOLTS | SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks. | Alessio Colucci, Andreas Steininger, Muhammad Shafique |
| 2024 | IOLTS | EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis. | Alessio Colucci, Andreas Steininger, Muhammad Shafique |
| 2023 | DSD | Towards Resilient Quasi Delay Insensitive Conditional Control Elements. | Zaheer Tabassam, Andreas Steininger |
| 2023 | ETS | SET Effects on Quasi Delay Insensitive and Synchronous Circuits. | Zaheer Tabassam, Andreas Steininger |
| 2022 | DDECS | On SAT-Based Model Checking of Speed-Independent Circuits. | Florian Huemer, Robert Najvirt, Andreas Steininger |
| 2022 | DDECS | AFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. | Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger |
| 2022 | DSD | Towards Resilient QDI Pipeline Implementations. | Zaheer Tabassam, Andreas Steininger |
| 2022 | IROS | enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. | Alessio Colucci, Andreas Steininger, Muhammad Shafique |
| 2021 | DDECS | Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. | Raghda El Shehaby, Andreas Steininger |
| 2021 | DSD | An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. | Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger |
| 2020 | DDECS | Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. | Wolfgang Duer, Andreas Steininger |
| 2020 | ICCD | On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. | Raghda El Shehaby, Andreas Steininger |
| 2019 | ECRTS | Sustainable Security & Safety: Challenges and Opportunities. | Andrew Paverd, Marcus Vlp, Ferdinand Brasser, Matthias Schunter, N. Asokan, Ahmad-Reza Sadeghi, Paulo Jorge Esteves Verssimo, Andreas Steininger, Thorsten Holz |
| 2019 | ITC | International Symposium on Design and Diagnostics of Electronic Circuits and Systems. | Zoran Stamenkovic, Alberto Bosio, Gyrgy Cserey, Ondrej Novk, Witold A. Pleskacz, Luks Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjakov |
| 2018 | DDECS | Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. | Florian Huemer, Thomas Polzer, Andreas Steininger |
| 2017 | DDECS | Measuring metastability using a time-to-digital converter. | Thomas Polzer, Florian Huemer, Andreas Steininger |
| 2017 | DSD | Setup for an Experimental Study of Radiation Effects in 65nm CMOS. | Bernhard Fritz, Andreas Steininger, Vclav Simek, Varadan Savulimedu Veeravalli |
| 2016 | DDECS | A general approach for comparing metastable behavior of digital CMOS gates. | Thomas Polzer, Andreas Steininger |
| 2016 | DSD | Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? | Andreas Steininger, Robert Najvirt, Jrgen Maier |
| 2016 | DSD | Design and Physical Implementation of a Target ASIC for SET Experiments. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2016 | ETS | Study of a delayed single-event effect in the Muller C-element. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2016 | ICCD | A new coding scheme for fault tolerant 4-phase delay-insensitive codes. | Florian Huemer, Jakob Lechner, Andreas Steininger |
| 2015 | DDECS | Containment of Metastable Voltages in FPGAs. | Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger |
| 2015 | DSD | Measuring the Distribution of Metastable Upsets over Time. | Thomas Polzer, Andreas Steininger |
| 2015 | DSD | Enhanced Metastability Characterization Based on AC Analysis. | Thomas Polzer, Andreas Steininger |
| 2015 | DSD | Reliable and Continuous Measurement of SET Pulse Widths. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2015 | ICCD | Methods for analysing and improving the fault resilience of delay-insensitive codes. | Jakob Lechner, Andreas Steininger, Florian Huemer |
| 2014 | DATE | A tree arbiter cell for high speed resource sharing in asynchronous environments. | Syed Rameez Naqvi, Andreas Steininger |
| 2014 | DDECS | Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. | Jrgen Maier, Andreas Steininger |
| 2014 | ICCD | Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. | Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel |
| 2013 | DDECS | A Multi-Credit Flow Control scheme for asynchronous NoCs. | Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger |
| 2013 | DSD | Digital Late-Transition Metastability Simulation Model. | Thomas Polzer, Andreas Steininger |
| 2013 | SAFECOMP | Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. | Stefan Resch, Andreas Steininger, Christoph Scherrer |
| 2012 | DATE | Designing FlexRay-based automotive architectures: A holistic OEM approach. | Paul Milbredt, Michael Gla, Martin Lukasiewycz, Andreas Steininger, Jrgen Teich |
| 2012 | DDECS | Radiation-tolerant combinational gates - an implementation based comparison. | Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2012 | DSD | Protecting an Asynchronous NoC against Transient Channel Faults. | Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger |
| 2012 | DSD | Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. | Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid |
| 2011 | FMICS | Past Time LTL Runtime Verification for Microcontroller Binary Code. | Thomas Reinbacher, Jrg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski |
| 2011 | RV | Automated Test-Trace Inspection for Microcontroller Binary Code. | Thomas Reinbacher, Jrg Brauer, Daniel Schachinger, Andreas Steininger, Stefan Kowalewski |
| 2010 | DDECS | A deterministic approach for hardware fault injection in asynchronous QDI logic. | Werner Friesenbichler, Thomas Panhofer, Andreas Steininger |
| 2010 | DDECS | Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. | Marcus Jeitler, Jakob Lechner, Andreas Steininger |
| 2010 | DSN | Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. | Thomas Panhofer, Werner Friesenbichler, Andreas Steininger |
| 2009 | DATE | Remote measurement of local oscillator drifts in FlexRay networks. | Eric Armengaud, Andreas Steininger |
| 2009 | DDECS | On the role of the power supply as an entry for common cause faults - An experimental analysis. | Peter Tummeltshammer, Andreas Steininger |
| 2009 | DSD | Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. | Werner Friesenbichler, Andreas Steininger |
| 2009 | DSD | On the Risk of Fault Coupling over the Chip Substrate. | Peter Tummeltshammer, Andreas Steininger |
| 2009 | DSN | Power supply induced common cause faults-experimental assessment of potential countermeasures. | Peter Tummeltshammer, Andreas Steininger |
| 2009 | SSS | A Metastability-Free Multi-synchronous Communication Scheme for SoCs. | Thomas Polzer, Thomas Handl, Andreas Steininger |
| 2008 | CVPR | Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. | Kristian Ambrosch, Martin Humenberger, Wilfried Kubinger, Andreas Steininger |
| 2008 | DSD | Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. | Gottfried Fuchs, Matthias Fgger, Ulrich Schmid, Andreas Steininger |
| 2007 | CVPR | Hardware implementation of an SAD based stereo vision algorithm. | Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, Andreas Steininger |
| 2007 | ETFA | The effect of quartz drift on convergence-average based clock synchronization. | Eric Armengaud, Andreas Steininger, Alexander Hanzlik |
| 2007 | PRDC | A Fail-Silent Reconfigurable Superscalar Processor. | Thomas Kottke, Andreas Steininger |
| 2006 | DSD | Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods. | Martin Delvai, Andreas Steininger |
| 2006 | DSN | A Reconfigurable Generic Dual-Core Architecture. | Thomas Kottke, Andreas Steininger |
| 2006 | ETFA | Automatic Parameter Identi cation in FlexRay based Automotive Communication Networks. | Eric Armengaud, Andreas Steininger, Martin Horauer |
| 2005 | ETFA | Efficient stimulus generation for testing embedded distributed systems the FlexRay example. | Eric Armengaud, Andreas Steininger, Martin Horauer |
| 2005 | ITC | A structured approach for the systematic test of embedded automotive communication systems. | Eric Armengaud, Florian Rothensteiner, Andreas Steininger, Roman Pallierer, Martin Horauer, Martin Zauner |
| 2003 | ECRTS | Processor Support for Temporal Predictability - The SPEAR Design Example. | Martin Delvai, Wolfgang Huber, Peter P. Puschner, Andreas Steininger |
| 2002 | ICCD | Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example. | Andreas Steininger, Johann Vilanek |
| 1991 | ECRTS | Can the advantages of RISC be utilized in real time systems? | Andreas Steininger, Herbert Schweinzer |