| 2024 | VLSID | FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2020 | FCCM | Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2020 | FPGA | Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. | Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar |
| 2019 | ACSSC | FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2019 | VLSID | VLSI Architectures for Jacobi Symbol Computation. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2018 | ISCAS | A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. | Avishek Sinha Roy, Anindya Sundar Dhar |
| 2018 | VLSID | High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2017 | HiPC | Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2016 | VLSID | Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2015 | ISCAS | New triple-transistor based defect-tolerant systems for reliable digital architectures. | Atin Mukherjee, Anindya Sundar Dhar |
| 2012 | VLSID | Random Access Analog Memory (RA2M) for Video Signal Application. | Nilanjan Chattaraj, Anindya Sundar Dhar |
| 2006 | ISCAS | Sampled analog architecture for 2-D DCT. | C. Thakkar, Anindya Sundar Dhar |
| 2005 | VLSID | Design Issues in Switched Capacitor Ladder Filters. | Arindam Basu, Anindya Sundar Dhar |
| 2004 | ISCAS | Digital controlled analog architecture for DCT and DST using capacitor switching. | Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar |
| 2004 | ISCAS | Sampled analog architecture for DCT and DST. | Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar |
| 2004 | VLSID | Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. | Ashis Kumar Mal, Anindya Sundar Dhar |
| 2001 | ICASSP | CORDIC realization of the transversal adaptive filter using a trigonometric LMS algorithm. | Mrityunjoy Chakraborty, Anindya Sundar Dhar, Suraiya Pervin |
| 1992 | VLSID | An Array Architecture for Computing KLT Basis Vectors. | Anindya Sundar Dhar |