Antonio J. Acosta
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
4
Active years
1993–2024
Best venue rank
C
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | DSD | Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher. | Francisco Eugenio Potestad-Ordez, Erica Tena-Snchez, Virginia Ziga-Gonzlez, Antonio J. Acosta |
| 2015 | ISCAS | DPA vulnerability analysis on Trivium stream cipher using an optimized power model. | Erica Tena-Snchez, Antonio J. Acosta |
| 2014 | DSD | Low-Power Differential Logic Gates for DPA Resistant Circuits. | Erica Tena-Snchez, Javier Castro-Ramirez, Antonio J. Acosta |
| 2010 | ISCAS | Optimization of clock-gating structures for low-leakage high-performance applications. | Javier Castro-Ramirez, Pilar Parra Fernndez, Antonio J. Acosta |
| 2007 | ISCAS | Asymmetric clock driver for improved power and noise performances. | Javier Castro-Ramirez, Pilar Parra Fernndez, Manuel Valencia-Barrero, Antonio J. Acosta |
| 2007 | ISCAS | Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. | Renato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider |
| 2001 | DATE | Analog/mixed-signal IP modeling for design reuse. | Natividad Martnez Madrid, Eduardo J. Peralas, Antonio J. Acosta, Adoracin Rueda |
| 2001 | DATE | HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. | Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero |
| 2001 | ISCAS | Gate-level simulation of CMOS circuits using the IDDM model. | Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero |
| 2000 | DATE | A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. | Eduardo J. Peralas, Antonio J. Acosta, Adoracin Rueda, Jos L. Huertas |
| 2000 | ISCAS | Inertial and degradation delay model for CMOS logic gates. | Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia |
| 2000 | ISCAS | VHDL-based behavioural description of pipeline ADCs. | Eduardo J. Peralas, Antonio J. Acosta, Adoracin Rueda, Jos L. Huertas |
| 1998 | VTS | Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. | T. A. Garca, Antonio J. Acosta, Jos L. Huertas, J. M. Mora, J. Ramos |
| 1993 | ISCAS | A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. | Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, Jos Luis Huertas, Rafael Domnguez-Castro |