Asit K. Mishra

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

Venues

Active years

2008–2019

Best venue rank

Where they publish

Papers

32 indexed papers, newest first.

Year	Venue	Title	Authors
2019	ISCA	Opportunistic computing in GPU architectures.	Ashutosh Pattnaik, Xulong Tang, Onur Kayiran, Adwait Jog, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das
2018	FCCM	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs.	Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	FPGA	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs: (Abstract Only).	Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	FPGA	A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.	Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2018	FPGA	In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018	FPL	In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2018	ICLR	Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy.	Asit K. Mishra, Debbie Marr
2018	ICLR	WRPN: Wide Reduced-Precision Networks.	Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2017	ASPDAC	Fine-grained accelerators for sparse machine learning workloads.	Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr
2017	FPL	High performance binary neural networks on the Xeon+FPGA™ platform.	Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2016	DATE	Hardware accelerator for analytics of sparse data.	Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr
2016	FPL	Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.	Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr
2016	HPCA	ScalCore: Designing a core for voltage scalability.	Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra
2015	CASES	A sparse matrix vector multiply accelerator for support vector machine.	Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr
2014	HPCA	Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks.	Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas
2013	ASPLOS	OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance.	Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das
2013	DAC	A heterogeneous multiple network-on-chip design: an application-aware approach.	Asit K. Mishra, Onur Mutlu, Chita R. Das
2013	HPCA	Runnemede: An architecture for Ubiquitous High-Performance Computing.	Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benot Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu
2013	ISCA	Orchestrated scheduling and prefetching for GPGPUs.	Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das
2012	DAC	Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.	Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Chita R. Das
2011	DAC	An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.	Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan
2011	HPCA	ACCESS: Smart scheduling for asymmetric cache CMPs.	Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar R. Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das
2011	ISCA	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2011	ISCA	A case for heterogeneous on-chip interconnects for CMPs.	Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2011	SIGMETRICS	METE: meeting end-to-end QoS in multicores through system-wide resource management.	Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut T. Kandemir, Chita R. Das
2010	SC	CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors.	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
2010	SIGMETRICS	Coordinated power management of voltage islands in CMPs.	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das
2009	HPCA	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2009	MICRO	A case for dynamic frequency tuning in on-chip networks.	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2009	SC	A case for integrated processor-cache partitioning in chip multiprocessors.	Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir
2008	HPCA	Performance and power optimization through data compression in Network-on-Chip architectures.	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das
2008	ISCA	MIRA: A Multi-layered On-Chip Interconnect Router Architecture.	Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das