Avaneendra Gupta
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
1996–1999
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1999 | VLSID | Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1998 | ICCAD | Optimal 2-D cell layout with integrated transistor folding. | Avaneendra Gupta, John P. Hayes |
| 1997 | DAC | CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1997 | VLSID | A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1996 | DATE | XPRESS: A Cell Layout Generator with Integrated Transistor Folding. | Avaneendra Gupta, Siang-Chun The, John P. Hayes |
| 1996 | ICCAD | Width minimization of two-dimensional CMOS cells using integer programming. | Avaneendra Gupta, John P. Hayes |