| 2026 | VLSID | FPGA Optimized Pipelined Modulo Computation Architecture Leveraging Primitive Instantiation and Placement Constraints for Efficient Logic Packing. | Suprabhat Bhattacharjee, Ayan Palchaudhuri |
| 2025 | VLSID | Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion. | Soham Adhikary, Ayan Palchaudhuri |
| 2025 | VLSID | Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA. | Santosh Kumar, Ayan Palchaudhuri |
| 2024 | HiPC | Exploring Efficient BCD to Binary Conversion Architecture Alternatives on FPGA. | Santosh Kumar, Ayan Palchaudhuri |
| 2024 | VLSID | FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2020 | FCCM | Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2020 | FPGA | Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. | Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar |
| 2019 | ACSSC | FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2019 | VLSID | VLSI Architectures for Jacobi Symbol Computation. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2018 | VLSID | High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2017 | HiPC | Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2016 | VLSID | Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2015 | DSD | Automated Design of High Performance Integer Arithmetic Cores on FPGA. | Ayan Palchaudhuri, Rajat Subhra Chakraborty, Durga Prasad Sahoo |