| 2021 | VTC | Isolation of redundant and mixed-critical automotive applications: effects on the system architecture. | Alessandro Frigerio, Bart Vermeulen, Kees Goossens |
| 2020 | DATE | A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles. | Tjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman rs, Pieter J. van der Perk, Andrei Sergeevich Terechko, Bart Vermeulen |
| 2019 | DSN | Component-Level ASIL Decomposition for Automotive Architectures. | Alessandro Frigerio, Bart Vermeulen, Kees Goossens |
| 2018 | SAFECOMP | A Generic Method for a Bottom-Up ASIL Decomposition. | Alessandro Frigerio, Bart Vermeulen, Kees Goossens |
| 2016 | DATE | Overview of Health Monitoring Techniques for Reliability. | Abhijit K. Deb, Bart Vermeulen, Luc van Dijk |
| 2014 | DATE | Startup error detection and containment to improve the robustness of hybrid FlexRay networks. | Alexander Kordes, Bart Vermeulen, Abhijit K. Deb, Michael G. Wahl |
| 2014 | DATE | Transient errors resiliency analysis technique for automotive safety critical applications. | Sujan Pandey, Bart Vermeulen |
| 2012 | ICCD | Architecture and design flow for a debug event distribution interconnect. | Arnaldo Azevedo, Bart Vermeulen, Kees Goossens |
| 2011 | DATE | Optimal scheduling of switched FlexRay networks. | Thijs Schenkelaars, Bart Vermeulen, Kees Goossens |
| 2010 | DSD | On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. | Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen |
| 2010 | ETFA | Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks. | Paul Milbredt, Bart Vermeulen, Gkhan Tabanoglu, Martin Lukasiewycz |
| 2010 | ETS | A distributed architecture to check global properties for post-silicon debug. | Erik Larsson, Bart Vermeulen, Kees Goossens |
| 2010 | ETS | New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. | Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen |
| 2010 | SAFECOMP | INDEXYS, a Logical Step beyond GENESYS. | Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, Gyrgy Csertn, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler |
| 2009 | DATE | A high-level debug environment for communication-centric debug. | Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad |
| 2008 | ITC | Integration of Hardware Assertions in Systems-on-Chip. | Jeroen Geuzebroek, Bart Vermeulen |
| 2007 | ASPDAC | A Run-Time Memory Protection Methodology. | Udaya Seshua, Nagaraju Bussa, Bart Vermeulen |
| 2007 | ETS | Communication-Centric SoC Debug Using Transactions. | Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek |
| 2005 | ITC | Test and debug features of the RTO7 chip. | Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld |
| 2004 | DAC | Automatic generation of breakpoint hardware for silicon debug. | Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel |
| 2004 | ITC | Trends in Testing Integrated Circuits. | Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge |
| 2003 | DATE | Creating Value Through Test. | Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Mller |
| 2003 | ITC | Optimal Interconnect ATPG Under a Ground-Bounce Constraint. | Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen |
| 2002 | ETS | Data invalidation analysis for scan-based debug on multiple-clock system chips. | Sandeep Kumar Goel, Bart Vermeulen |
| 2002 | ITC | Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. | Sandeep Kumar Goel, Bart Vermeulen |
| 2002 | ITC | TAPS All Over My Chips! So Now What Do I Do? | Bart Vermeulen |
| 2002 | ITC | EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. | Bart Vermeulen, Tom Waayers, Sjaak Bakker |
| 2002 | ITC | Core-Based Scan Architecture for Silicon Debug. | Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel |
| 2002 | VTS | Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? | Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark |
| 2001 | ITC | Test and debug strategy of the PNX8525 Nexperia | Bart Vermeulen, Steven Oostdijk, Frank Bouwman |
| 1999 | ITC | Silicon debug: scan chains alone are not enough. | Gert-Jan van Rootselaar, Bart Vermeulen |