| 2005 | VLSID | The High Walls have Crumpled. | C. L. Liu |
| 2001 | DAC | Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. | Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang |
| 2001 | DATE | Binary decision diagram with minimum expected path length. | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu |
| 2000 | DAC | A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. | Junhyung Um, Taewhan Kim, C. L. Liu |
| 2000 | ICCAD | Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
| 2000 | ISLPED | Noise-aware power optimization for on-chip interconnect. | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
| 1999 | DAC | Crosstalk Minimization Using Wire Perturbations. | Prashant Saxena, C. L. Liu |
| 1999 | DATE | Logic Transformation for Low Power Synthesis. | Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu |
| 1999 | ICCAD | Implication graph based domino logic synthesis. | Ki-Wook Kim, C. L. Liu, Sung-Mo Kang |
| 1999 | ICCAD | Optimal allocation of carry-save-adders in arithmetic optimization. | Junhyung Um, Taewhan Kim, C. L. Liu |
| 1999 | ISCAS | An efficient data path synthesis algorithm for behavioral-level power optimization. | Chaeryung Park, Taewhan Park, C. L. Liu |
| 1999 | VLSID | The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. | Prashant Saxena, Peichen Pan, C. L. Liu |
| 1999 | RTSS | From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. | C. L. Liu |
| 1998 | ICCAD | Architecture driven circuit partitioning. | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
| 1998 | ICCAD | Power invariant vector sequence compaction. | Ali Pinar, C. L. Liu |
| 1998 | ICCAD | A performance-driven layer assignment algorithm for multiple interconnect trees. | Prashant Saxena, C. L. Liu |
| 1998 | ISLPED | Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. | Ki-Seok Chung, C. L. Liu |
| 1998 | ISLPED | Low power logic synthesis under a general delay model. | Unni Narayanan, Peichen Pan, C. L. Liu |
| 1997 | DAC | Low Power FPGA Design - A Re-engineering Approach. | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
| 1997 | ICCAD | Low power logic synthesis for XOR based circuits. | Unni Narayanan, C. L. Liu |
| 1997 | ICCD | Optimal Clock Period Clustering for Sequential Circuits with Retiming. | Arvind K. Karandikar, Peichen Pan, C. L. Liu |
| 1996 | DAC | Desensitization for Power Reduction in Sequential Circuits. | Xiangfeng Chen, Peichen Pan, C. L. Liu |
| 1996 | DAC | Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. | Peichen Pan, C. L. Liu |
| 1996 | DATE | Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. | Anmol Mathur, C. L. Liu |
| 1996 | DATE | A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. | Srilata Raman, C. L. Liu, Larry G. Jones |
| 1996 | EuroPar | A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. | Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu |
| 1996 | FPGA | Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. | Peichen Pan, C. L. Liu |
| 1996 | ICCAD | An algorithm for synthesis of system-level interface circuits. | Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu |
| 1995 | DAC | Partial Scan with Pre-selected Scan Signals. | Peichen Pan, C. L. Liu |
| 1995 | FPGA | Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. | Anmol Mathur, Kuang-Chien Chen, C. L. Liu |
| 1995 | ICCAD | Re-engineering of timing constrained placements for regular architectures. | Anmol Mathur, Kuang-Chien Chen, C. L. Liu |
| 1994 | DAC | Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. | Yachyang Sun, C. L. Liu |
| 1994 | ICCAD | Minimum crosstalk switchbox routing. | Tong Gao, C. L. Liu |
| 1994 | ICCAD | Compression-relaxation: a new approach to performance driven placement for regular architectures. | Anmol Mathur, C. L. Liu |
| 1994 | ICCAD | Area minimization for hierarchical floorplans. | Peichen Pan, Weiping Shi, C. L. Liu |
| 1993 | DAC | Utilization of Multiport Memories in Data Path Synthesis. | Taewhan Kim, C. L. Liu |
| 1993 | DAC | Optimal Graph Constraint Reduction for Symbolic Layout Compaction. | Peichen Pan, Sai-keung Dong, C. L. Liu |
| 1993 | ICCAD | Minimum crosstalk channel routing. | Tong Gao, C. L. Liu |
| 1993 | ICCAD | Routing for symmetric FPGAs and FPICs. | Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu |
| 1992 | DAC | A Performance Driven Macro-Cell Placement Algorithm. | Tong Gao, Pravin M. Vaidya, C. L. Liu |
| 1992 | ICCAD | Area minimization for general floorplans. | Peichen Pan, C. L. Liu |
| 1992 | ICCD | An Area Minimizer for Floorplans with L-Shaped Regions. | Yachyang Sun, C. L. Liu |
| 1991 | ICCAD | A New Performance Driven Placement Algorithm. | Tong Gao, Pravo M. Vaidya, C. L. Liu |
| 1991 | ICCAD | A Scheduling Algorithm for Conditional Resource Sharing. | Taewhan Kim, Jane W.-S. Liu, C. L. Liu |
| 1991 | ICCAD | A Channel Router for Single Layer Customization Technology. | Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu |
| 1990 | DAC | General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. | Jason Cong, Bryan Preas, C. L. Liu |
| 1989 | DAC | Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. | Ran Libeskind-Hadas, C. L. Liu |
| 1989 | ICCAD | Constrained floorplan design for flexible blocks. | Sai-keung Dong, Jason Cong, C. L. Liu |
| 1988 | DAC | A New Approach to the Pin Assignment Problem. | Xianji Yao, Masaaki Yamada, C. L. Liu |
| 1988 | ICCAD | Over-the-cell channel routing. | Jingsheng Cong, C. L. Liu |
| 1988 | ICCAD | A new formulation of yield enhancement problems for reconfigurable chips. | Nany Hasan, Jason Cong, C. L. Liu |
| 1987 | DAC | Array Optimization for VLSI Synthesis. | D. F. Wong, C. L. Liu |
| 1986 | DAC | A new algorithm for floorplan design. | D. F. Wong, C. L. Liu |
| 1984 | DAC | A branch and bound algorithm for optimal pla folding. | James L. Lewandowski, C. L. Liu |
| 1983 | DAC | A new channel routing problem. | Hon Wai Leong, C. L. Liu |
| 1982 | DAC | Optimal bipartite folding of PLA. | Jack R. Egan, C. L. Liu |
| 1976 | PERFORMANCE | Deterministic Job Scheduling in Computing Systems. | C. L. Liu |
| 1972 | FOCS | Optimal Scheduling on Multi-Processor Computing Systems | C. L. Liu |
| 1971 | FOCS | Analysis of Sorting Algorithms | C. L. Liu |
| 1966 | FOCS | Pair Algebra and Its Application | C. L. Liu |
| 1964 | FOCS | Sequential-machine realization using feedback shift registers | C. L. Liu |