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Chih-Tsun Huang

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

34

Venues

10

Active years

1997–2025

Best venue rank

A*

Where they publish

Papers

34 indexed papers, newest first.

YearVenueTitleAuthors
2025ISCASA Low-complexity and Reconfigurable Design for Nonlinear Function Approximation in Transformers.Qi-Xian Wu, Shu-Sian Teng, Ming-Der Shieh, Chih-Tsun Huang, Juin-Ming Lu
2025ITCTest and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks.Po-Sheng Chiu, Chih-Yu Hsu, Chih-Tsun Huang, Jing-Jia Liou
2023ICCDMultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy.Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu
2019DATEData Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators.Hao-Ning Wu, Chih-Tsun Huang
2016ETSIoT: Source of test challenges.Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singele, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
2015ASPDACDesign of a scalable many-core processor for embedded applications.Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou
2015ASPDACApplication-level embedded communication tracer for many-core systems.Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien
2013ISCADesign of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures.Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou
2011ASPDACTurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler.Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung
2011DACReliability analysis and improvement for multi-level non-volatile memories with soft information.Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang
2011DACA low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2010ISCASHigh-performance architecture for Elliptic Curve Cryptography over binary field.Jyu-Yuan Lai, Tzu-Yu Hung, Kai-Hsiang Yang, Chih-Tsun Huang
2008DACAn embedded infrastructure of debug and trace interface for the DSP platform.Ming-Chang Hsieh, Chih-Tsun Huang
2007ASPDACA High-Throughput Low-Power AES Cipher for Network Applications.Shin-Yi Lin, Chih-Tsun Huang
2006DACA network security processor design based on an integrated SOC design and test platform.Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
2006DATEOptimization of regular expression pattern matching circuits on FPGA.Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
2005ASPDACA configurable AES processor for enhanced security.Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
2005ASPDACDesign and test of a scalable security processor.Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2005VTSA BIST Scheme for FPGA Interconnect Delay Faults.Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
2004ASPDACAn HMAC processor with integrated SHA-1 and MD5 algorithms.Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
2004ITCAn SOC Test Integration Platform and Its Industrial Realization.Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
2003ASPDACA highly efficient AES cipher chip.Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
2003ASPDACDesign of a scalable RSA and ECC crypto-processor.Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
2003ICCADFAME: A Fault-Pattern Based Memory Failure Analysis Framework.Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2003ITCFault Pattern Oriented Defect Diagnosis for Memories.Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
2003VTSTest and Diagnosis of Word-Oriented Multiport Memories.Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2002ITCDiagonal Test and Diagnostic Schemes for Flash Memorie.Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2002VTSRAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
2001DACSimulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
2001ITCMarch-based RAM diagnosis algorithms for stuck-at and coupling faults.Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2000ASPDACA programmable built-in self-test core for embedded memories.Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
2000ICCADError Catch and Analysis for Semiconductor Memories Using March Tests.Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
2000VTSSimulation-Based Test Algorithm Generation for Random Access Memories.Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
1997DATEHigh-speed C-testable systolic array design for Galois-field inversion.Chih-Tsun Huang, Cheng-Wen Wu