| 2025 | ISCAS | A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity. | Binbin Chen, Heyu Ren, Wenjun Gong, Liangjian Lyu, Chuanjin Richard Shi |
| 2025 | ISCAS | A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N. | Sirou Li, Weijia Zeng, Kaiyun Cao, Liangjian Lyu, Chuanjin Richard Shi |
| 2021 | ISCAS | A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse. | Chang Liu, Chun Zhao, Chuanjin Richard Shi |
| 2020 | DATE | ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM. | Yitu Wang, Fan Chen, Linghao Song, Chuanjin Richard Shi, Hai Helen Li, Yiran Chen |
| 2020 | ISCAS | A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. | Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi |
| 2019 | ASPDAC | A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. | Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi |
| 2019 | IJCAI | Hierarchical Representation Learning for Bipartite Graphs. | Chong Li, Kunyang Jia, Dan Shen, Chuanjin Richard Shi, Hongxia Yang |
| 2019 | ISCAS | A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. | Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi |
| 2019 | ISCAS | A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. | Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi |
| 2018 | DAC | Exploring the programmability for deep learning processors: from architecture to tensorization. | Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, Chuanjin Richard Shi |
| 2018 | ECCV | Constrained Optimization Based Low-Rank Approximation of Deep Neural Networks. | Chong Li, Chuanjin Richard Shi |
| 2018 | ISCAS | Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. | Ailing Piao, Aili Wang, Chuanjin Richard Shi |
| 2016 | ISCAS | A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing. | Aili Wang, Allen Waters, Chuanjin Richard Shi |
| 2016 | ISCAS | Highly time-interleaved noise-shaped SAR ADC with reconfigurable order. | Allen Waters, Aili Wang, Chuanjin Richard Shi |
| 2010 | ISCAS | Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology. | Chuanjin Richard Shi |
| 2008 | ASPDAC | Symmetry-aware placement with transitive closure graphs for analog layout design. | Lihong Zhang, Chuanjin Richard Shi, Yingtao Jiang |
| 2008 | ISCAS | A 6-11GHz multi-phase VCO design with active inductors. | Yu-Te Liao, Chuanjin Richard Shi |
| 2008 | ISCAS | A quantum-dot light-harvesting architecture using deterministic phase control. | Cherry Wakayama, Wolf Kohn, Zelda B. Zabinsky, Chuanjin Richard Shi |
| 2007 | ASPDAC | A Graph Reduction Approach to Symbolic Circuit Analysis. | Guoyong Shi, Weiwei Chen, Chuanjin Richard Shi |
| 2007 | ICCD | Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. | Ming Su, Lili Zhou, Chuanjin Richard Shi |
| 2007 | ICCD | Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. | Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi |
| 2006 | ASPDAC | A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. | Zhao Li, Chuanjin Richard Shi |
| 2006 | ASPDAC | A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. | Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi |
| 2006 | ICCAD | Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. | Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi |
| 2006 | ISCAS | Improved automatic differentiation method for efficient model compiler. | Bo Hu, Chuanjin Richard Shi |
| 2005 | ASPDAC | An FPGA implementation of low-density parity-check code decoder with multi-rate capability. | Lei Yang, Manyuan Shen, Hui Liu, Chuanjin Richard Shi |
| 2005 | DAC | Template-driven parasitic-aware optimization of analog integrated circuit layouts. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi |
| 2005 | DATE | An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. | Zhao Li, Chuanjin Richard Shi |
| 2005 | GLOBECOM | VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity. | Lei Yang, Hui Liu, Chuanjin Richard Shi |
| 2005 | ICCAD | Fast-yet-accurate PVT simulation by combined direct and iterative methods. | Bo Hu, Chuanjin Richard Shi |
| 2005 | ISCAS | Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. | Bo Hu, Zhao Li, Lili Zhou, Chuanjin Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe |
| 2005 | VLSID | Automatic Device Layout Generation for Analog Layout Retargeting. | Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi |
| 2004 | ASPDAC | Hierarchical extraction and verification of symmetry constraints for analog layout automation. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi |
| 2004 | ASPDAC | Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. | Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi |
| 2004 | ASPDAC | CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. | Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, Chuanjin Richard Shi |
| 2004 | ASPDAC | Parametric reduced order modeling for interconnect analysis. | Guoyong Shi, Chuanjin Richard Shi |
| 2004 | DAC | Correct-by-construction layout-centric retargeting of large analog designs. | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi |
| 2004 | DATE | Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. | Bo Wan, Chuanjin Richard Shi |
| 2004 | ISCAS | A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. | Zhao Li, Chuanjin Richard Shi |
| 2003 | ASPDAC | Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. | Sheldon X.-D. Tan, Chuanjin Richard Shi |
| 2003 | DAC | Symbolic analysis of analog circuits with hard nonlinearity. | Alicia Manthe, Zhao Li, Chuanjin Richard Shi |
| 2003 | DATE | Symbolic Analysis of Nonlinear Analog Circuits. | Alicia Manthe, Zhao Li, Chuanjin Richard Shi, Kartikeya Mayaram |
| 2003 | ICCAD | SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. | Zhao Li, Chuanjin Richard Shi |
| 2003 | ICCAD | FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. | Lei Yang, Chuanjin Richard Shi |
| 2003 | ISCAS | Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. | Sambuddha Bhattacharya, Chuanjin Richard Shi |
| 2003 | ISCAS | Automatic analog layout retargeting for new processes and device sizes. | Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi |
| 2001 | DAC | Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. | Sheldon X.-D. Tan, Chuanjin Richard Shi |
| 2001 | ICCD | Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits. | Dragos Lungeanu, Chuanjin Richard Shi |
| 2001 | ICCD | Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis. | Alicia Manthe, Chuanjin Richard Shi |
| 2000 | ASPDAC | Analog-testability analysis by determinant-decision-diagrams based symbolic analysis. | Tao Pi, Chuanjin Richard Shi |
| 2000 | ASPDAC | Symbolic circuit-noise analysis and modeling with determinant decision diagrams. | Xiang-Dong Tan, Chuanjin Richard Shi |
| 2000 | DAC | Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. | Tao Pi, Chuanjin Richard Shi |
| 2000 | DATE | Layout Compaction for Yield Optimization via Critical Area Minimization. | Youcef Bourai, Chuanjin Richard Shi |
| 2000 | DATE | Parallel and Distributed VHDL Simulation. | Dragos Lungeanu, Chuanjin Richard Shi |
| 1999 | ASPDAC | Symmetry Detection for Automatic Analog-Layout Recycling. | Youcef Bourai, Chuanjin Richard Shi |
| 1999 | ASPDAC | Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. | Xiang-Dong Tan, Chuanjin Richard Shi |
| 1999 | DAC | Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. | Xiang-Dong Tan, Chuanjin Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan |
| 1999 | DATE | Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. | Xiang-Dong Tan, Chuanjin Richard Shi |
| 1999 | ICCAD | Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. | Dragos Lungeanu, Chuanjin Richard Shi |
| 1998 | ASPDAC | Automatic Test Generation for Linear Analog Circuits under Parameter Variations. | Chuanjin Richard Shi, Michael W. Tian |
| 1998 | DATE | Efficient DC Fault Simulation of Nonlinear Analog Circuits. | Michael W. Tian, Chuanjin Richard Shi |
| 1998 | VTS | Nonlinear Analog DC Fault Simulation by One-Step Relaxation. | Michael W. Tian, Chuanjin Richard Shi |
| 1997 | DAC | Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances. | Michael W. Tian, Chuanjin Richard Shi |
| 1997 | ICCAD | Symbolic analysis of large analog circuits with determinant decision diagrams. | Chuanjin Richard Shi, Xiang-Dong Tan |
| 1997 | VTS | Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. | Nihal J. Godambe, Chuanjin Richard Shi |
| 1995 | ASPDAC | A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems. | Chuanjin Richard Shi, Janusz A. Brzozowski |