| 2025 | ASPDAC | Standard Cell Layout Generation: Review, Challenges, and Future Works. | Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang |
| 2025 | ICCAD | (Invited Paper) Overview of 2025 CAD Contest at ICCAD. | Chung-Kuan Cheng, Shao-Yun Fang, Yi-Yu Liu, Tsun-Ming Tseng |
| 2025 | ICCAD | SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing. | Chung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin |
| 2024 | ICCAD | Overview of 2024 CAD contest at ICCAD. | Shao-Yun Fang, Yi-Yu Liu, Chung-Kuan Cheng, Tsun-Ming Tseng |
| 2024 | ICCAD | SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture. | Sheng-Tan Huang, Ying-Jie Jiang, Shao-Yun Fang, Chung-Kuan Cheng |
| 2022 | ASPDAC | Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. | Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz |
| 2022 | DAC | Placement initialization via a projected eigenvector algorithm: late breaking results. | Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang |
| 2021 | ASPDAC | A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs. | Ting-Chou Lin, Devon J. Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng |
| 2021 | ASPDAC | GRA-LPO: Graph Convolution Based Leakage Power Optimization. | Uday Mallappa, Chung-Kuan Cheng |
| 2021 | ICCD | CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. | Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo |
| 2020 | ASPDAC | SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm. | Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng |
| 2020 | ICCAD | A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. | Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park |
| 2020 | ISCAS | Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility. | Chung-Kuan Cheng, Daeyeal Lee, Dongwon Park |
| 2018 | DAC | Adaptive sensitivity analysis with nonlinear power load modeling. | Po-Ya Hsu, Chun-Han Yao, Yuwei Wang, Chung-Kuan Cheng |
| 2018 | DAC | Fast and precise routability analysis with conditional design rules. | Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng |
| 2018 | ICCAD | Transient circuit simulation for differential algebraic systems using matrix exponential. | Pengwen Chen, Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang |
| 2017 | ICCAD | Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation. | Xinyuan Wang, Hao Zhuang, Chung-Kuan Cheng |
| 2015 | DAC | An algorithmic framework for efficient large-scale circuit simulation using exponential integrators. | Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng |
| 2014 | DAC | ePlace: Electrostatics Based Placement Using Nesterov's Method. | Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-H. Huang, Chin-Chi Teng, Chung-Kuan Cheng |
| 2014 | DAC | MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks. | Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng |
| 2013 | ASPDAC | Layer minimization in escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng |
| 2012 | ASPDAC | Character design and stamp algorithms for Character Projection Electron-Beam Lithography. | Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham |
| 2012 | ICCAD | A fast time-domain EM-TCAD coupled simulation framework via matrix exponential. | Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong |
| 2012 | ICCAD | Circuit simulation via matrix exponential method for stiffness handling and parallel processing. | Shih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng |
| 2011 | DATE | A block-diagonal structured model reduction scheme for power grid networks. | Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong |
| 2011 | ISCAS | A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation. | Shih-Hung Weng, Peng Du, Chung-Kuan Cheng |
| 2010 | ASPDAC | An adaptive parallel flow for power distribution network simulation using discrete Fourier transform. | Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng |
| 2010 | ASPDAC | On-chip power network optimization with decoupling capacitors and controlled-ESRs. | Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng |
| 2009 | ARITH | Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders. | Chung-Kuan Cheng |
| 2009 | ASPDAC | Parallel transistor level circuit simulation using domain decomposition methods. | He Peng, Chung-Kuan Cheng |
| 2009 | ASPDAC | High performance on-chip differential signaling using passive compensation for global communication. | Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng |
| 2009 | ASPDAC | Noise minimization during power-up stage for a multi-domain power network. | Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng |
| 2009 | DAC | Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. | Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng |
| 2009 | DATE | Reliability aware through silicon via planning for 3D stacked ICs. | Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen |
| 2009 | DATE | Parallel transistor level full-chip circuit simulation. | He Peng, Chung-Kuan Cheng |
| 2009 | ICCD | 3D stacked power distribution considering substrate coupling. | Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich |
| 2009 | ICCD | Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations. | Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng |
| 2008 | ASPDAC | High performance current-mode differential logic. | Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto |
| 2008 | ASPDAC | Timing-power optimization for mixed-radix Ling adders by integer linear programming. | Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng |
| 2008 | DAC | Low power passive equalizer optimization using tritonic step response. | Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng |
| 2008 | DATE | Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. | Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng |
| 2008 | HOTI | Low Power Passive Equalizer Design for Computer Memory Links. | Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng |
| 2008 | ICCAD | A novel fixed-outline floorplanner with zero deadspace for hierarchical design. | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
| 2008 | ICCAD | Efficient and accurate eye diagram prediction for high speed signaling. | Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh |
| 2008 | ICCAD | Advancing supercomputer performance through interconnection topology synthesis. | Yi Zhu, Michael B. Taylor, Scott B. Baden, Chung-Kuan Cheng |
| 2008 | ICCD | On-chip high performance signaling using passive compensation. | Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng |
| 2007 | ASPDAC | Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. | Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis |
| 2007 | ASPDAC | Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. | Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen |
| 2007 | ASPDAC | An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. | Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris |
| 2007 | BIBE | Exploring Cardioneural Signals from Noninvasive ECG Measurement. | Amirali Shayan Arani, Yi Zhu, Yi-Ning Cheng, Chung-Kuan Cheng, Shien-Fong Lin, Peng-Sheng Chen |
| 2007 | ICCD | FPGA global routing architecture optimization using a multicommodity flow approach. | Yuanfang Hu, Yi Zhu, Michael B. Taylor, Chung-Kuan Cheng |
| 2007 | ICCD | Passive compensation for high performance inter-chip communication. | Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng |
| 2007 | ICCD | Fast power network analysis with multiple clock domains. | Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng |
| 2007 | ISCAS | Fast Transient Simulation of Lossy Transmission Lines. | He Peng, Chung-Kuan Cheng |
| 2007 | ISCAS | Incremental Power Impedance Optimization Using Vector Fitting Modeling. | Wanping Zhang, Chung-Kuan Cheng |
| 2006 | ASPDAC | Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton |
| 2006 | ASPDAC | An unconditional stable general operator splitting method for transistor level transient analysis. | Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh |
| 2006 | BIBE | Noninvasive Study of the Human Heart using Independent Component Analysis. | Yi Zhu, Tong Lee Chen, Wanping Zhang, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng |
| 2006 | DAC | Communication latency aware low power NoC synthesis. | Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng |
| 2006 | DAC | Efficient escape routing for hexagonal array of high density I/Os. | Rui Shi, Chung-Kuan Cheng |
| 2006 | FPGA | An iterative division algorithm for FPGAs. | Jianhua Liu, Michael Chang, Chung-Kuan Cheng |
| 2006 | ICCAD | Layer minimization of escape routing in area array packaging. | Renshen Wang, Rui Shi, Chung-Kuan Cheng |
| 2006 | ICCAD | Timing model reduction for hierarchical timing analysis. | Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng |
| 2005 | ASPDAC | A multi-level transmission line network approach for multi-giga hertz clock distribution. | Hongyu Chen, Chung-Kuan Cheng |
| 2005 | ASPDAC | Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? | Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen |
| 2005 | ASPDAC | Integrated algorithmic logical and physical design of integer multiplier. | Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng |
| 2005 | ASPDAC | Constructing zero-deficiency parallel prefix adder of minimum depth. | Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham |
| 2005 | ASPDAC | Efficient transient simulation for transistor-level analysis. | Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh |
| 2005 | ICCAD | Improving the efficiency of static timing analysis with false paths. | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris |
| 2005 | ICCD | Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. | Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris |
| 2005 | ICCD | Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. | Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng |
| 2005 | ISCAS | VLSI block placement with alignment constraints based on corner block list. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng |
| 2005 | ISCAS | Performance constrained floorplanning based on partial clustering [IC layout]. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng |
| 2004 | ASPDAC | Optimal planning for mesh-based power distribution. | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang |
| 2004 | ASPDAC | A buffer planning algorithm with congestion optimization. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ASPDAC | Buffer allocation algorithm with consideration of routing congestion. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ASPDAC | A multiple level network approach for clock skew minimization with process variations. | Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng |
| 2004 | FPGA | Fast adders in modern FPGAs. | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris |
| 2003 | ASPDAC | A buffer planning algorithm based on dead space redistribution. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | The Y-architecture: yet another on-chip interconnect solution. | Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng |
| 2003 | ASPDAC | UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. | Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | RCLK-VJ network reduction with Hurwitz polynomial approximation. | Zhanhai Qin, Chung-Kuan Cheng |
| 2003 | DAC | An algebraic multigrid solver for analytical placement with layout based clustering. | Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu |
| 2003 | DAC | Dynamic global buffer planning optimization based on detail block locating and congestion analysis. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | DAC | Realizable parasitic reduction using generalized Y-Delta transformation. | Zhanhai Qin, Chung-Kuan Cheng |
| 2003 | DAC | Power network analysis using an adaptive algebraic multigrid approach. | Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng |
| 2003 | ICCAD | The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao |
| 2003 | ICCAD | An Algorithmic Approach for Generic Parallel Adders. | Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng |
| 2003 | ISCAS | Evaluating a bounded slice-line grid assignment in O(nlogn) time. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ISCAS | Arbitrary convex and concave rectilinear block packing based on corner block list. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu |
| 2002 | ICCD | Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. | Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham |
| 2002 | ICCD | Physical Planning Of On-Chip Interconnect Architectures. | Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng |
| 2002 | VLSID | Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | ASPDAC | Toward better wireload models in the presence of obstacles. | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt |
| 2001 | ASPDAC | VLSI floorplanning with boundary constraints based on corner block list. | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | DAC | Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | ICCAD | Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. | Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai |
| 2000 | ASPDAC | A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. | Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng |
| 2000 | DAC | Fast post-placement rewiring using easily detectable functional symmetries. | Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska |
| 2000 | DAC | Block placement with symmetry constraints based on the O-tree non-slicing representation. | Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng |
| 2000 | ICCAD | Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
| 2000 | ICCAD | Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. | Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher |
| 1999 | ASPDAC | A Performance-Driven I/O Pin Routing Algorithm. | Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen |
| 1999 | DAC | An O-Tree Representation of Non-Slicing Floorplan and Its Applications. | Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura |
| 1999 | ICCAD | RLC interconnect delay estimation via moments of amplitude and phase response. | Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng |
| 1998 | DAC | Extending Moment Computation to 2-Port Circuit Representations. | Fang-Jou Liu, Chung-Kuan Cheng |
| 1997 | ASPDAC | A building block placement tool. | Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng |
| 1997 | ASPDAC | A new layout-driven timing model for incremental layout optimization. | Fang-Jou Liu, John Lillis, Chung-Kuan Cheng |
| 1997 | DAC | A Network Flow Approach for Hierarchical Tree Partitioning. | Ming-Ter Kuo, Chung-Kuan Cheng |
| 1997 | DAC | Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. | John Lillis, Chung-Kuan Cheng |
| 1997 | DAC | Cluster Refinement for Block Placement. | Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng |
| 1996 | DAC | Network Partitioning into Tree Hierarchies. | Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng |
| 1996 | DAC | New Spectral Linear Placement and Clustering Approach. | Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng |
| 1996 | DAC | New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho |
| 1996 | DAC | Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. | Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng |
| 1995 | ASPDAC | Performance driven multiple-source bus synthesis using buffer insertion. | Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1995 | DAC | Performance-Driven Partitioning Using a Replication Graph Approach. | Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu |
| 1995 | FCCM | Routability improvement using dynamic interconnect architecture. | Jianmin Li, Chung-Kuan Cheng |
| 1995 | ICCAD | Linear decomposition algorithm for VLSI design applications. | Jianmin Li, John Lillis, Chung-Kuan Cheng |
| 1995 | ICCAD | Optimal wire sizing and buffer insertion for low power and a generalized delay model. | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1995 | ICCAD | A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. | Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng |
| 1995 | ICCD | Simple tree-construction heuristics for the fanout problem . | Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng |
| 1995 | ISCAS | Finite State Machine Decomposition for I/O Minimization. | Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng |
| 1995 | ISLPED | Optimization of power dissipation and skew sensitivity in clock buffer synthesis. | Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1994 | DAC | Circuit Partitioning for Huge Logic Emulation Systems. | Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof |
| 1994 | DAC | Data Flow Partitioning for Clock Period and Latency Minimization. | Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng |
| 1994 | ICCAD | Skew sensitivity minimization of buffered clock tree. | Jae Chung, Chung-Kuan Cheng |
| 1993 | DAC | Untitled record | Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau |
| 1993 | DAC | Performance-Driven Steiner Tree Algorithm for Global Routing. | Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang |
| 1993 | DAC | An Efficient Timing-Driven Global Routing Algorithm. | Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh |
| 1993 | DAC | Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. | So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo |
| 1993 | ICCAD | An efficient algorithm for the net matching problem. | Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita |
| 1993 | ICCAD | Performance-driven partitioning using retiming and replication. | Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku |
| 1992 | DAC | A Wire Length Estimation Technique Utilizing Neighborhood Density Equations. | Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau |
| 1992 | DAC | FARM: An Efficient Feed-Through Pin Assignment Algorithm. | Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh |
| 1992 | ICCAD | An optimal probe testing algorithm for the connectivity verification of MCM substrates. | So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu |
| 1992 | ICCAD | A probabilistic multicommodity-flow solution to circuit clustering problems. | Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1991 | DAC | A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm. | Robert C. Carden IV, Chung-Kuan Cheng |
| 1991 | DAC | A General Purpose Multiple Way Partitioning Algorithm. | Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1990 | ICCAD | A Two-Level Two-Way Partitioning Algorithm. | Yen-Chuen Wei, Chung-Kuan Cheng |
| 1990 | IPCO | Ancestor Tree for Arbitrary Multi-Terminal Cut Functions. | Chung-Kuan Cheng, T. C. Hu |
| 1989 | ICCAD | Towards efficient hierarchical designs by ratio cut partitioning. | Yen-Chuen Wei, Chung-Kuan Cheng |
| 1988 | DAC | Improved Channel Routing by Via Minimization and Shifting. | Chung-Kuan Cheng, David N. Deutsch |