| 2015 | FPL | A technology mapper for depth-constrained FPGA logic cells. | Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne |
| 2014 | FPL | A survey of open source processors for FPGAs. | Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang |
| 2014 | FPL | Exploring architecture parameters for dual-output LUT based FPGAs. | Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang |
| 2014 | FPL | A semi-supervised modeling approach for performance characterization of FPGA architectures. | Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin |
| 2013 | FCCM | A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. | Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So |
| 2013 | FPL | Timing-constrained minimum area/power FPGA memory mapping. | Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang |
| 2012 | FPGA | Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). | Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So |
| 2011 | FCCM | A Model for Peak Matrix Performance on FPGAs. | Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong |
| 2011 | FPL | A Model for Matrix Multiplication Performance on FPGAs. | Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong |
| 2009 | FPL | Operation scheduling for FPGA-based reconfigurable computers. | Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So |