Cyrille Chavet
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
7
Active years
2007–2024
Best venue rank
Multiconference
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | FIE | WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU). | Klaus Hofmann, Ferdinand Keil, David Riehl, Alicja Michalowska-Forsyth, Nikolaus Czepl, Sarah Woywod, Dominik Zupan, Mario R. Casu, Carlo Ricciardi, Massimo Violante, Mariagrazia Graziano, Yuri Ardesi, Fabrizio Mo, Dominik Berger, Sabine Sill, Volker Visotschnig, Panagiota Morfouli, Liliana Prejbeanu, Katell Morin-Allory, Cyrille Chavet, Davide Bucci, Skandar Basrour, Jean-Christophe Crebier, Nhu-Huan Nguyen, Ernesto Quisbert-Trujillo, Christian Deflix, Isabelle Corbett-Etchevers, Johannes Sturm, Jens Peter Konrath, Ulla Birnbacher, Thomas Klinger, Wolfgang Werth, Jorge Fernandes, Marcelino B. Santos, Antonio Rubio, Alba Pags-Zamora, Josep Pegueroles, Jordi Salazar, Beatriz Otero, J. Manuel Moreno, X. Aragones, Israel Martin, Aleix Sole, Dunja Suttnig, Julia Calabro, Floriberto Lima, Eric Jouseau, Franois Cerisier, Cristian Rivier, Sepp Eisenriegler, Harald Reichl, Miroslav Macan, Dubravko Kruselj, Mladen Puskaric, Mirjana Tatalovic, Vinko Zelenicic, Bernd Deutschmann |
| 2020 | ICASSP | Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards. | Hassan Harb, Cyrille Chavet |
| 2020 | ISCAS | Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. | Ghita Harcha, Vianney Laptre, Cyrille Chavet, Philippe Coussy |
| 2019 | ICASSP | Solving Memory Access Conflicts in LTE-4G Standard. | Cyrille Chavet, Fabrice Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy |
| 2016 | DATE | A dynamically reconfigurable ECC decoder architecture. | Awais Sani, Philippe Coussy, Cyrille Chavet |
| 2015 | DATE | In-place memory mapping approach for optimized parallel hardware interleaver architectures. | Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani |
| 2015 | ISCAS | Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. | Hugues Wouafo, Cyrille Chavet, Philippe Coussy |
| 2014 | ICASSP | Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. | Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy |
| 2013 | FPL | Dynamic branch prediction for high-level synthesis. | Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo |
| 2013 | ICASSP | On-chip implementation of memory mapping algorithm to support flexible decoder architecture. | Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet |
| 2012 | DSD | OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. | Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini |
| 2011 | ICASSP | A methodology based on Transportation problem modeling for designing parallel interleaver architectures. | Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin |
| 2011 | ISCAS | An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. | Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin |
| 2010 | ICASSP | Static Address Generation Easing: a design methodology for parallel interleaver architectures. | Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin |
| 2010 | ISCAS | A memory mapping approach for parallel interleaver design with multiples read and write accesses. | Cyrille Chavet, Philippe Coussy |
| 2007 | ICCAD | A design flow dedicated to multi-mode architectures for DSP applications. | Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin |
| 2007 | ISCAS | A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. | Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin |