| 2017 | VLSID | Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. | Prasenjit Biswas, D. M. H. Walker |
| 2014 | VLSID | Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. | Kun Bian, D. M. H. Walker, Sunil P. Khatri |
| 2012 | ICCD | Maximizing crosstalk-induced slowdown during path delay test. | Dibakar Gope, D. M. H. Walker |
| 2011 | VTS | Levelized low cost delay test compaction considering IR-drop induced power supply noise. | Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker |
| 2008 | VTS | Dynamic Compaction for High Quality Delay Test. | Zheng Wang, D. M. H. Walker |
| 2006 | ITC | Comparison of Delay Tests on Silicon. | Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore |
| 2006 | ITC | Power Supply Noise in Delay Testing. | Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger |
| 2005 | ITC | A vector-based approach for power supply noise analysis in test compaction. | Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
| 2005 | ITC | I | Bin Xue, D. M. H. Walker |
| 2005 | VTS | Static Compaction of Delay Tests Considering Power Supply Noise. | Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker |
| 2004 | ASPDAC | Longest path selection for delay test under process variation. | Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi |
| 2004 | ITC | K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. | Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran |
| 2004 | VLSID | Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. | Sagar S. Sabade, D. M. H. Walker |
| 2004 | VTS | A Statistical Fault Coverage Metric for Realistic Path Delay Faults. | Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi |
| 2004 | VTS | On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. | Sagar S. Sabade, D. M. H. Walker |
| 2003 | ITC | An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. | Wangqi Qiu, D. M. H. Walker |
| 2003 | VLSID | Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. | Sagar S. Sabade, D. M. H. Walker |
| 2003 | VTS | A Circuit Level Fault Model for Resistive Opens and Bridges. | Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
| 2003 | VTS | Use of Multiple IDDQ Test Metrics for Outlier Identification. | Sagar S. Sabade, D. M. H. Walker |
| 2002 | VLSID | Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. | Sagar S. Sabade, D. M. H. Walker |
| 2002 | VTS | Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. | Sagar S. Sabade, D. M. H. Walker |
| 2001 | ASPDAC | An efficient solution to the storage correspondence problem for large sequential circuits. | Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee |
| 2001 | ITC | A practical built-in current sensor for I_DDQ testing. | Hoki Kim, D. M. H. Walker, David Colby |
| 2001 | ITC | Improved wafer-level spatial analysis for I_DDQ limit setting. | Sagar S. Sabade, D. M. H. Walker |
| 2001 | ITC | FedEx - a fast bridging fault extractor. | Zoran Stanojevic, D. M. H. Walker |
| 2000 | ITC | Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. | Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler |
| 2000 | VTS | Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. | Byungwoo Choi, D. M. H. Walker |
| 2000 | VTS | PROBE: A PPSFP Simulator for Resistive Bridging Faults. | Chul Young Lee, D. M. H. Walker |
| 1999 | ITC | Resistive bridge fault modeling, simulation and test generation. | Vijay R. Sar-Dessai, D. M. H. Walker |
| 1999 | ITC | Design for Yield and Reliability is MORE Important Than DFT. | D. M. H. Walker |
| 1999 | VTS | Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. | Debashis Nayak, D. M. H. Walker |
| 1998 | FPGA | Bridging Fault Detection in FPGA Interconnects Using | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
| 1998 | ITC | Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
| 1996 | ITC | Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. | Yuyun Liao, D. M. H. Walker |
| 1996 | ITC | Test Generation for Global Delay Faults. | G. M. Luong, D. M. H. Walker |
| 1996 | VTS | Improvement of SRAM-based failure analysis using calibrated Iddq testing. | Hari Balachandran, D. M. H. Walker |
| 1996 | VTS | Optimal voltage testing for physically-based faults. | Yuyun Liao, D. M. H. Walker |
| 1995 | ITC | Yiel Learning via Functional Test Data. | Young-Jun Kwon, D. M. H. Walker |
| 1995 | ITC | IC Performance Prediction System. | V. Ramakrishnan, D. M. H. Walker |
| 1993 | VTS | Estimation of reject ratio in testing of combinatorial circuits. | Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly |
| 1991 | DAC | A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. | D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas |