Debjit Sinha
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
22
Venues
7
Active years
2004–2021
Best venue rank
A*
Where they publish
Papers
22 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | DATE | Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure. | Ravi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile |
| 2020 | DAC | Statistical Timing Analysis considering Multiple-Input Switching. | Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams |
| 2016 | DAC | A distributed timing analysis framework for large designs. | Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran |
| 2016 | DAC | Statistical path tracing in timing graphs. | Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya |
| 2016 | DAC | Practical statistical static timing analysis with current source models. | Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala |
| 2016 | ICCAD | Generation and use of statistical timing macro-models considering slew and load variability. | Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey |
| 2016 | VLSID | Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. | Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma |
| 2014 | ICCAD | TAU 2014 contest on removing common path pessimism during timing analysis. | Jin Hu, Debjit Sinha, Igor Keller |
| 2013 | DAC | Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization. | Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan |
| 2012 | DAC | Reversible statistical | Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov |
| 2012 | DAC | Timing analysis with nonseparable statistical and deterministic variations. | Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran |
| 2008 | DAC | Driver waveform computation for timing analysis with multiple voltage threshold driver models. | Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta |
| 2008 | ICCAD | Constrained aggressor set selection for maximum coupling noise. | Debjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam |
| 2007 | VLSID | Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. | Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou |
| 2006 | DATE | Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. | Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou |
| 2006 | ICCAD | A timing dependent power estimation framework considering coupling. | Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou |
| 2006 | MICRO | Yield-Aware Cache Architectures. | Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou |
| 2005 | ASPDAC | Yield driven gate sizing for coupling-noise reduction under uncertainty. | Debjit Sinha, Hai Zhou |
| 2005 | ICCAD | Statistical gate sizing for timing yield optimization. | Debjit Sinha, Narendra V. Shenoy, Hai Zhou |
| 2005 | ICCAD | A unified framework for statistical timing analysis with coupling and multiple input switching. | Debjit Sinha, Hai Zhou |
| 2004 | FPGA | An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. | Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee |
| 2004 | ICCAD | Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. | Debjit Sinha, Hai Zhou |