| 2017 | CEC | On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks. | Franc Brglez, Borko Boskovic, Janez Brest |
| 2005 | DAC | Effective bounding techniques for solving unate and binate covering problems. | Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez |
| 2003 | SAT | A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation. | Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez |
| 2001 | DAC | A Universal Client for Distributed Networked Design and Computing. | Franc Brglez, Hemang Lavana |
| 2000 | ICCD | OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. | Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan |
| 1999 | ALENEX | Heuristics and Experimental Design for Bigraph Crossing Number Minimization. | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh |
| 1999 | ISCAS | Design of experiments in CAD: context and new data sets for ISCAS'99. | Franc Brglez, Rolf Drechsler |
| 1999 | ISCAS | Equivalence classes of circuit mutants for experimental design. | Debabrata Ghosh, Franc Brglez |
| 1999 | ISCAS | Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. | Justin E. Harlow III, Franc Brglez |
| 1999 | ISCAS | User-configurable experimental design flows on the web: the ISCAS'99 experiments. | Hemang Lavana, Franc Brglez, Robert B. Reese |
| 1999 | ISCAS | Evaluating iterative improvement heuristics for bigraph crossing minimization. | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh |
| 1998 | DATE | Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. | Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III |
| 1998 | FMCAD | Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. | Justin E. Harlow III, Franc Brglez |
| 1998 | ICCAD | Design of experiments in BDD variable ordering: lessons learned. | Justin E. Harlow III, Franc Brglez |
| 1997 | DAC | Executable Workflows: A Paradigm for Collaborative Design on the Internet. | Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski |
| 1997 | Group | Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments. | Hemang Lavana, Amit Khetawat, Franc Brglez |
| 1995 | ICCAD | PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. | Roman Kuznar, Franc Brglez |
| 1995 | VTS | Detectable perturbations: a paradigm for technology-specific multi-fault test generation. | Andrej Zemva, Franc Brglez |
| 1994 | DAC | Clock Period Optimization During Resource Sharing and Assignment. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1994 | DAC | Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1994 | DAC | Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. | Roman Kuznar, Franc Brglez, Baldomir Zajc |
| 1994 | ICCAD | Provably correct high-level timing analysis without path sensitization. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1993 | DAC | Cost Minimization of Partitions into Multiple Devices. | Roman Kuznar, Franc Brglez, Krzysztof Kozminski |
| 1992 | DAC | Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. | Ulf Schlichtmann, Franc Brglez, Michael Hermann |
| 1992 | ITC | Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. | Matthew Melton, Franc Brglez |
| 1991 | ICCD | Partitioning Sequential Circuits for Logic Optimization. | Sujit Dey, Franc Brglez, Gershon Kedem |
| 1990 | DAC | Corolla Based Circuit Partitioning and Resynthesis. | Sujit Dey, Franc Brglez, Gershon Kedem |
| 1990 | ICCD | Built-in self-test with weighted random pattern hardware. | Franc Brglez, Clay S. Gloster Jr., Gershon Kedem |
| 1990 | RSP | OASIS: a silicon compiler for semi-custom design. | Gershon Kedem, Franc Brglez, Krzysztof Kozminski |
| 1989 | ITC | Hardware-Based Weighted Random Pattern Generation for Boundary Scan. | Franc Brglez, Gershon Kedem, Clay Gloster |
| 1989 | ITC | A Framework and Method for Hierarchical Test Generation. | John D. Calhoun, Franc Brglez |
| 1988 | ICCD | A modular scan-based testability system. | Franc Brglez, David Bryan, John D. Calhoun, Robert Lisanke |
| 1988 | ICCD | McMAP: a fast technology mapping procedure for multi-level logic synthesis. | Robert Lisanke, Franc Brglez, Gershon Kedem |
| 1988 | ITC | Boundary Scan with Cellular-Based Built-In Self-Test. | Clay Gloster, Franc Brglez |
| 1987 | DAC | Accelerated Transition Fault Simulation. | Michael H. Schultz, Franc Brglez |
| 1985 | ITC | A Fast Fault Grader: Analysis and Applications. | Franc Brglez |
| 1985 | ITC | Fault Coverage Tools: Case Studies. | Franc Brglez |
| 1984 | ITC | Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. | Franc Brglez, Philip Pownall, Robert Hum |
| 1981 | DAC | A set of programs for MOS design. | G. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox |
| 1981 | ITC | Digital Signal Processing Considerations in Filter-Codec Testing. | Franc Brglez |