| 2026 | ASPLOS | Sequential Specifications for Precise Hardware Exceptions. | Yulun Yao, Drew Zagieboylo, Andrew C. Myers, G. Edward Suh |
| 2026 | HPCA | Leveraging ASIC AI Chips for Homomorphic Encryption. | Jianming Tong, Tianhao Huang, Jingtian Dang, Leo de Castro, Anirudh Itagi, Anupam Golder, Asra Ali, Jeremy Kun, Jevin Jiang, Arvind, G. Edward Suh, Tushar Krishna |
| 2026 | ICS | GPIR: Enabling Practical Private Information Retrieval with GPUs. | Hyesung Ji, Hyunah Yu, Jongmin Kim, Wonseok Choi, G. Edward Suh, Jung Ho Ahn |
| 2026 | ISPASS | Beyond Latency: A System-Level Characterization of MPC and FHE for PPML. | Pengzhi Huang, Kiwan Maeng, G. Edward Suh |
| 2025 | ASPLOS | Practical Federated Recommendation Model Learning Using ORAM with Controlled Privacy. | Jinyu Liu, Wenjie Xiong, G. Edward Suh, Kiwan Maeng |
| 2025 | HPCA | Efficient Memory Side-Channel Protection for Embedding Generation in Machine Learning. | Muhammad Umar, Akhilesh Parag Marathe, Monami Dutta Gupta, Shubham Jogprakash Ghosh, G. Edward Suh, Wenjie Xiong |
| 2025 | ICLR | AutoDAN-Turbo: A Lifelong Agent for Strategy Self-Exploration to Jailbreak LLMs. | Xiaogeng Liu, Peiran Li, G. Edward Suh, Yevgeniy Vorobeychik, Zhuoqing Mao, Somesh Jha, Patrick McDaniel, Huan Sun, Bo Li, Chaowei Xiao |
| 2025 | ICML | Trustworthy Machine Learning through Data-Specific Indistinguishability. | Hanshen Xiao, Zhen Yang, G. Edward Suh |
| 2025 | ISCA | Hermes: Algorithm-System Co-design for Efficient Retrieval-Augmented Generation At-Scale. | Michael Shen, Muhammad Umar, Kiwan Maeng, G. Edward Suh, Udit Gupta |
| 2025 | SP | Machine Learning with Privacy for Protected Attributes. | Saeed Mahloujifar, Chuan Guo, G. Edward Suh, Kamalika Chaudhuri |
| 2024 | ASPLOS | GPU-based Private Information Retrieval for On-Device Machine Learning Inference. | Maximilian Lam, Jeff Johnson, Wenjie Xiong, Kiwan Maeng, Udit Gupta, Yang Li, Liangzhen Lai, Ilias Leontiadis, Minsoo Rhu, Hsien-Hsin S. Lee, Vijay Janapa Reddi, Gu-Yeon Wei, David Brooks, G. Edward Suh |
| 2024 | ASPLOS | LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models. | Juntaek Lim, Youngeun Kwon, Ranggi Hwang, Kiwan Maeng, G. Edward Suh, Minsoo Rhu |
| 2024 | CCS | Formal Privacy Proof of Data Encoding: The Possibility and Impossibility of Learnable Encryption. | Hanshen Xiao, G. Edward Suh, Srinivas Devadas |
| 2024 | HPCA | LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. | Yueying Li, Nikita Lazarev, David Koufaty, Tenny Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou |
| 2023 | CCS | SpecVerilog: Adapting Information Flow Control for Secure Speculation. | Drew Zagieboylo, Charles Sherk, Andrew C. Myers, G. Edward Suh |
| 2023 | HPCA | AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks. | Mulong Luo, Wenjie Xiong, Geunbae Lee, Yueying Li, Xiaomeng Yang, Amy Zhang, Yuandong Tian, Hsien-Hsin S. Lee, G. Edward Suh |
| 2023 | ICLR | MACTA: A Multi-agent Reinforcement Learning Approach for Cache Timing Attacks and Detection. | Jiaxun Cui, Xiaomeng Yang, Mulong Luo, Geunbae Lee, Peter Stone, Hsien-Hsin S. Lee, Benjamin Lee, G. Edward Suh, Wenjie Xiong, Yuandong Tian |
| 2023 | ICLR | Mitigating Metastable Failures in Distributed Systems with Offline Reinforcement Learning. | Yueying Li, Daochen Zha, Tianjun Zhang, G. Edward Suh, Christina Delimitrou, Francis Y. Yan |
| 2023 | ICML | Cocktail Party Attack: Breaking Aggregation-Based Privacy in Federated Learning Using Independent Component Analysis. | Sanjay Kariyappa, Chuan Guo, Kiwan Maeng, Wenjie Xiong, G. Edward Suh, Moinuddin K. Qureshi, Hsien-Hsin S. Lee |
| 2022 | DAC | GuardNN: secure accelerator architecture for privacy-preserving deep learning. | Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh |
| 2022 | HPCA | SecNDP: Secure Near-Data Processing with Untrusted Memory. | Wenjie Xiong, Liu Ke, Dimitrije Jankov, Michael Kounavis, Xiaochen Wang, Eric Northup, Jie Amy Yang, Bilge Acun, Carole-Jean Wu, Ping Tak Peter Tang, G. Edward Suh, Xuan Zhang, Hsien-Hsin S. Lee |
| 2022 | ISCA | MGX: near-zero overhead memory protection for data-intensive accelerators. | Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh |
| 2022 | ISCA | SoftVN: efficient memory protection via software-provided version numbers. | Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh |
| 2022 | ISPASS | Characterization of MPC-based Private Inference for Transformer-based Models. | Yongqin Wang, G. Edward Suh, Wenjie Xiong, Benjamin Lefaudeux, Brian Knott, Murali Annavaram, Hsien-Hsin S. Lee |
| 2021 | ASPLOS | BCD deduplication: effective memory compression using partial cache-line deduplication. | Sungbo Park, Ingab Kang, Yaebin Moon, Jung Ho Ahn, G. Edward Suh |
| 2021 | ASPLOS | Sinan: ML-based and QoS-aware resource management for cloud microservices. | Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou |
| 2021 | CCS | Wireless Charging Power Side-Channel Attacks. | Alexander S. La Cour, Khurram K. Afridi, G. Edward Suh |
| 2020 | CGO | Efficient nursery sizing for managed languages on multi-core processors with shared caches. | Mohamed Ismail, G. Edward Suh |
| 2020 | ICLR | Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. | Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang |
| 2020 | ISIT | Strong Asymptotic Composition Theorems for Sibson Mutual Information. | Benjamin Wu, Aaron B. Wagner, G. Edward Suh, Ibrahim Issa |
| 2019 | DAC | Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. | Zhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang |
| 2019 | ISCA | TWiCe: preventing row-hammering by exploiting time window counters. | Eojin Lee, Ingab Kang, Sukhan Lee, G. Edward Suh, Jung Ho Ahn |
| 2019 | MICRO | Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. | Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh |
| 2018 | CCS | HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security. | Andrew Ferraiuolo, Mark Zhao, Andrew C. Myers, G. Edward Suh |
| 2018 | CCS | Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control. | Jed Liu, Joe Corbett-Davies, Andrew Ferraiuolo, Alexander Ivanov, Mulong Luo, G. Edward Suh, Andrew C. Myers, Mark E. Campbell |
| 2018 | DAC | Reverse engineering convolutional neural networks through side-channel information leaks. | Weizhe Hua, Zhiru Zhang, G. Edward Suh |
| 2018 | ICCAD | High-level synthesis with timing-sensitive information flow enforcement. | Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang |
| 2018 | MICRO | An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. | Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh |
| 2018 | SP | FPGA-Based Remote Power Side-Channel Attacks. | Mark Zhao, G. Edward Suh |
| 2017 | ASPLOS | Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis. | Andrew Ferraiuolo, Rui Xu, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
| 2017 | DAC | Secure Information Flow Verification with Mutable Dependent Types. | Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh |
| 2017 | HPCA | Secure Dynamic Memory Scheduling Against Timing Channel Attacks. | Yao Wang, Benjamin Wu, G. Edward Suh |
| 2016 | DAC | SecDCP: secure dynamic cache partitioning for efficient timing channel protection. | Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
| 2016 | HPCA | Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller. | Andrew Ferraiuolo, Yao Wang, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
| 2016 | ISLPED | Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation. | Taejoon Song, Daniel Lo, G. Edward Suh |
| 2016 | MICRO | Efficient data supply for hardware accelerators with prefetching and access/execute decoupling. | Tao Chen, G. Edward Suh |
| 2015 | ASPLOS | A Hardware Design Language for Timing-Sensitive Information-Flow Security. | Danfeng Zhang, Yao Wang, G. Edward Suh, Andrew C. Myers |
| 2015 | DAC | Improving worst-case cache performance through selective bypassing and register-indexed cache. | Mohamed Ismail, Daniel Lo, G. Edward Suh |
| 2015 | HPCA | Run-time monitoring with adjustable overhead using dataflow-guided filtering. | Daniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh |
| 2015 | MICRO | Execution time prediction for energy-efficient hardware accelerators. | Tao Chen, Alexander Rucker, G. Edward Suh |
| 2015 | MICRO | Prediction-guided performance-energy trade-off for interactive applications. | Daniel Lo, Taejoon Song, G. Edward Suh |
| 2014 | HPCA | Low-overhead and high coverage run-time race detection through selective meta-data management. | Ruirui C. Huang, Erik Halberg, Andrew Ferraiuolo, G. Edward Suh |
| 2014 | HPCA | Timing channel protection for a shared memory controller. | Yao Wang, Andrew Ferraiuolo, G. Edward Suh |
| 2014 | ICS | Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processing. | G. Edward Suh, Christopher W. Fletcher, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas |
| 2014 | ICS | Author retrospective for analytical cache models with applications to cache partitioning. | G. Edward Suh, George Kurian, Srinivas Devadas, Larry Rudolph |
| 2014 | RTAS | Slack-aware opportunistic monitoring for real-time systems. | Daniel Lo, Mohamed Ismail, Tao Chen, G. Edward Suh |
| 2013 | ISCA | Non-race concurrency bug detection through order-sensitive critical sections. | Ruirui C. Huang, Erik Halberg, G. Edward Suh |
| 2013 | SP | Hiding Information in Flash Memory. | Yinglei Wang, Wing-Kei S. Yu, Sarah Q. Xu, Edwin Kan, G. Edward Suh |
| 2012 | CCS | Hardware enhanced security. | Ruby B. Lee, Simha Sethumadhavan, G. Edward Suh |
| 2012 | CISS | On the performance of averaged optimal routing. | Nithin Michael, Ao Tang, G. Edward Suh |
| 2012 | DAC | Worst-case execution time analysis for parallel run-time monitoring. | Daniel Lo, G. Edward Suh |
| 2012 | DSN | High-performance parallel accelerator for flexible and efficient run-time monitoring. | Daniel Y. Deng, G. Edward Suh |
| 2012 | ICCD | Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis. | Mohamed Ismail, G. Edward Suh |
| 2012 | SP | Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints. | Yinglei Wang, Wing-Kei S. Yu, Shuo Wu, Greg Malysa, G. Edward Suh, Edwin Kan |
| 2011 | DSN | A non-volatile microcontroller with integrated floating-gate transistors. | Wing-Kei S. Yu, Shantanu Rajwade, Sung-En Wang, Bob Lian, G. Edward Suh, Edwin Kan |
| 2011 | FPL | FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric. | Daniel Lo, Greg Malysa, G. Edward Suh |
| 2011 | ICCD | Precise exception support for decoupled run-time monitoring architectures. | Daniel Y. Deng, G. Edward Suh |
| 2011 | ISCA | SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading. | Wing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh |
| 2010 | ASPLOS | Orthrus: efficient software integrity protection on multi-cores. | Ruirui C. Huang, Daniel Y. Deng, G. Edward Suh |
| 2010 | FPGA | Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). | Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh |
| 2010 | ISCA | IVEC: off-chip memory integrity protection for both security and reliability. | Ruirui C. Huang, G. Edward Suh |
| 2010 | MICRO | Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric. | Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh |
| 2009 | DAC | Hardware authentication leveraging performance limits in detailed simulations and emulations. | Daniel Y. Deng, Andrew H. Chan, G. Edward Suh |
| 2009 | ISCA | Application-aware deadlock-free oblivious routing. | Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas |
| 2008 | ICCAD | Diastolic arrays: throughput-driven reconfigurable computing. | Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas |
| 2007 | DAC | Physical Unclonable Functions for Device Authentication and Secret Key Generation. | G. Edward Suh, Srinivas Devadas |
| 2005 | ISCA | Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. | G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas |
| 2005 | SP | Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data. | Dwaine E. Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk, Srinivas Devadas |
| 2004 | ASPLOS | Secure program execution via dynamic information flow tracking. | G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas |
| 2003 | ASIACRYPT | Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking. | Dwaine E. Clarke, Srinivas Devadas, Marten van Dijk, Blaise Gassend, G. Edward Suh |
| 2003 | DAC | Embedded intelligent SRAM. | Prabhat Jain, G. Edward Suh, Srinivas Devadas |
| 2003 | HPCA | Caches and Hash Trees for Efficient Memory Integrity Verification. | Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas |
| 2003 | ICS | AEGIS: architecture for tamper-evident and tamper-resistant processing. | G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas |
| 2003 | MICRO | Efficient Memory Integrity Verification and Encryption for Secure Processors. | G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas |
| 2002 | HPCA | A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. | G. Edward Suh, Srinivas Devadas, Larry Rudolph |
| 2001 | ICS | Analytical cache models with applications to cache partitioning. | G. Edward Suh, Srinivas Devadas, Larry Rudolph |
| 2001 | JSSPP | Effects of Memory Performance on Parallel Job Scheduling. | G. Edward Suh, Larry Rudolph, Srinivas Devadas |