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Hiroshi Makino

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

6

Active years

1980–2014

Best venue rank

C

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2014DDECSThe LSI implementation of a memory based field programmable device for MCU peripherals.Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
2010ISCASAdiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
2008ISLPEDPost-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
2005ICCADWorst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2005ISCASA 3224-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
1998ISLPEDA low power SRAM using auto-backgate-controlled MT-CMOS.Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
1997ICCDA Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
1993ICCDA 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture.Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
1980COLINGAn Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences.Hiroshi Makino, Makoto Kizawa