| 2018 | ISCAS | Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. | Joan Barcel, Ivan de Pal, Sebasti A. Bota, Jaume Segura, Jaume Verd |
| 2018 | ISCAS | Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit. | Rafel Perell-Roig, Jaume Verd, Sebasti A. Bota, Jaume Segura |
| 2013 | IBPRIA | Automatic Detection and Characterization of Acoustic Plane-Wave Reflections Using Circular Microphone Arrays. | Maximo Cobos, Francesc J. Ferri, Ana M. Torres, Jaume Segura |
| 2011 | DATE | Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. | Bartomeu Alorda, Gabriel Torrens, Sebasti A. Bota, Jaume Segura |
| 2011 | DATE | An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. | Salvador Barcel, Xavier Gili, Sebasti A. Bota, Jaume Segura |
| 2010 | DATE | Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. | Bartomeu Alorda, Gabriel Torrens, Sebasti A. Bota, Jaume Segura |
| 2010 | IOLTS | Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. | Sebasti A. Bota, Gabriel Torrens, Bartomeu Alorda, Jaume Verd, Jaume Segura |
| 2009 | EATIS | Automated agent-based system for weather information. | Jaume Segura, Vicente R. Toms Lpez, Arturo Sez Esteve, Juan J. Martnez |
| 2009 | VTS | Stuck-Open Fault Leakage and Testing in Nanometer Technologies. | Julio Csar Vzquez, Vctor H. Champac, Chuck Hawkins, Jaume Segura |
| 2008 | IJCNN | Using stochastic logic for efficient pattern recognition analysis. | Jos Luis Rossell, Vincent Canals, Ivan de Pal, Jaume Segura |
| 2007 | DATE | Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. | Jos Luis Rossell, Carol de Benito, Sebasti A. Bota, Jaume Segura |
| 2007 | IOLTS | Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. | X. Cano, Sebasti A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura, Llus Garrido |
| 2006 | DATE | A compact model to identify delay faults due to crosstalk. | Jos Luis Rossell, Jaume Segura |
| 2006 | DDECS | CMOS Testing at the End of the Roadmap: Challenges and Opportunities. | Jaume Segura |
| 2006 | IJCNN | A Fully CMOS Low-Cost Chaotic Neural Network. | Jos Luis Rossell, Sebasti A. Bota, Vicent Canals, Ivan de Pal, Jaume Segura |
| 2006 | VTS | Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. | Sebasti A. Bota, M. Rosales, Jos Luis Rossell, Jaume Segura |
| 2005 | DATE | Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. | Sebasti A. Bota, M. Rosales, Jos Luis Rossell, Jaume Segura |
| 2005 | DATE | A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. | Jos Luis Rossell, Vicent Canals, Sebasti A. Bota, Ali Keshavarzi, Jaume Segura |
| 2005 | ETS | The anatomy of nanometer timing failures. | Chuck Hawkins, Jaume Segura |
| 2005 | IOLTS | A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. | Bartomeu Alorda, Sebasti A. Bota, Jaume Segura |
| 2004 | DATE | A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. | Jos Luis Rossell, Jaume Segura |
| 2004 | IOLTS | A BIST-based Charge Analysis for Embedded Memories. | Bartomeu Alorda, Vicent Canals, Ivan de Pal, Jaume Segura |
| 2004 | ITC | Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. | Sebasti A. Bota, M. Rosales, Jos Luis Rossell, Jaume Segura, Ali Keshavarzi |
| 2003 | IOLTS | An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. | Bartomeu Alorda, Jaume Segura |
| 2003 | ITC | CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. | Bartomeu Alorda, Brad Bloechel, Ali Keshavarzi, Jaume Segura |
| 2002 | DAC | A novel wavelet transform based transient current analysis for fault detection and localization. | Swarup Bhunia, Kaushik Roy, Jaume Segura |
| 2002 | IOLTS | An Off-Chip Sensor Circuit for On-Line Transient Current Testing. | Bartomeu Alorda, Andr Ivanov, Jaume Segura |
| 2002 | IOLTS | A BICS for CMOS Opamps by Monitoring the Supply Current Peak. | Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio Garca |
| 2002 | ITC | Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. | Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura |
| 2002 | ITC | GHz Testing and Its Fuzzy Targets. | Chuck Hawkins, Jaume Segura |
| 2002 | ITC | Parametric Failures in CMOS ICs - A Defect-Based Analysis. | Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins |
| 2002 | VTS | Challenges in Nanometric Technology Scaling: Trends and Projections. | Jaume Segura, Vivek De, Ali Keshavarzi |
| 2001 | ICCAD | Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. | Jos Luis Rossell, Jaume Segura |
| 2001 | VTS | Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. | Ivan de Pal, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden |
| 2000 | IOLTS | On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. | Bartomeu Alorda, Ivan de Pal, Jaume Segura, T. Miller |
| 1999 | ETS | Experimental results on BIC sensors for transient current testing. | Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio Garca-Moreno |
| 1999 | VTS | Analyzing the Need for ATPG Targeting GOS Defects. | Eugeni Isern, Miquel Roca, Jaume Segura |
| 1995 | DATE | A built-in quiescent current monitor for CMOS VLSI circuits. | Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura |
| 1995 | ITC | A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. | Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins |