| 2013 | CSCWD | Efficient custom instruction generation based on characterizing of basic blocks. | Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinian Bian |
| 2013 | CSCWD | Automatic enhanced CDFG generation based on runtime instrumentation. | Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao |
| 2013 | FCCM | Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. | Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian |
| 2013 | FPL | FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. | Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian |
| 2012 | ICCAD | ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. | Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian |
| 2011 | ASPDAC | Pruning-based trace signal selection algorithm. | Kang Zhao, Jinian Bian |
| 2011 | CSCWD | Instruction-level hardware/software partition through DFG exploration. | Kang Zhao, Jinian Bian |
| 2011 | CSCWD | A fast recursive detailed routing algorithm for hierarchical FPGAs. | Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai |
| 2010 | CSCWD | An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. | Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian |
| 2010 | DATE | Behavioral level dual-vth design for reduced leakage power with thermal awareness. | Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian |
| 2010 | ITC | Mutation-based diagnostic test generation for hardware design error diagnosis. | Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong |
| 2009 | ASPDAC | Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. | Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao |
| 2009 | ASPDAC | Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. | Junbo Yu, Qiang Zhou, Jinian Bian |
| 2009 | CSCWD | Random stimulus generation with self-tuning. | Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong |
| 2008 | ASPDAC | Low power clock buffer planning methodology in F-D placement for large scale circuit design. | Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian |
| 2008 | CSCWD | Cache miss reduction through hardware-assisted loop optimization. | Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto |
| 2008 | FPL | MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. | Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong |
| 2008 | ICCAD | A novel fixed-outline floorplanner with zero deadspace for hierarchical design. | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
| 2007 | CSCWD | A Management System of Metropolis Energy Information. | Hui Zhang, Jinian Bian |
| 2007 | CSCWD | A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. | Kang Zhao, Jinian Bian, Sheqin Dong |
| 2007 | DAC | EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. | Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao |
| 2006 | CSCWD | Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. | Shujun Deng, Weimin Wu, Jinian Bian |
| 2006 | CSCWD | Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. | Shujun Deng, Weimin Wu, Jinian Bian |
| 2006 | CSCWD | An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. | Yawen Niu, Jinian Bian, Haili Wang, Kun Tong |
| 2006 | CSCWD | AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. | Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu |
| 2006 | CSCWD | Universal data model platform: the data-centric evolution for system level codesign. | Kun Tong, Jinian Bian, Haili Wang |
| 2005 | ASPDAC | System-level architectural exploration using allocation-on-demand technique. | Qiang Wu, Jinian Bian, Hongxi Xue |
| 2005 | CSCWD | iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration. | Haili Wang, Jinian Bian, Qiang Wu, Yunfeng Wang |
| 2005 | CSCWD | Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs. | Jianzhou Zhao, Jinian Bian, Weimin Wu |
| 2005 | ISCAS | A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani |
| 2005 | ISCAS | Interconnect delay optimization via high level re-synthesis after floorplanning. | Yunfeng Wang, Jinian Bian, Xianlong Hong |
| 2004 | COMPSAC | PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. | Jianzhou Zhao, Jinian Bian, Weimin Wu |
| 2000 | ASPDAC | IBAW: an implication-tree based alternative-wiring logic transformation algorithm. | Wangning Long, Yu-Liang Wu, Jinian Bian |
| 1999 | ASPDAC | FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. | Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong |
| 1997 | ASPDAC | VIDE: a visual VHDL integrated design environment. | Jinian Bian, Hongxi Xue, Ming Su |