Kai-Chiang Wu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
39
Venues
18
Active years
2004–2026
Best venue rank
A*
Where they publish
Papers
39 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | AAAI | SkipCat: Rank-Maximized Low-Rank Compression of Large Language Models via Shared Projection and Block Skipping. | Yu-Chen Lu, Sheng-Feng Yu, Hui-Hsien Weng, Pei-Shuo Wang, Yu-Fang Hu, Liang Hung-Chun, Hung-Yueh Chiang, Kai-Chiang Wu |
| 2025 | EMNLP | FLRC: Fine-grained Low-Rank Compressor for Efficient LLM Inference. | Yu-Chen Lu, Chong-Yan Chen, Chi-Chih Chang, Yu-Fang Hu, Kai-Chiang Wu |
| 2025 | FPGA | Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. | Endri Taka, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora, Diana Marculescu |
| 2025 | GECCO | Integrating Neural Architecture Search and Rematerialization for Efficient On-Device Learning. | Chih-Ling Chen, Kai-Chiang Wu, Ning-Chi Huang |
| 2025 | ICCAD | Invited Paper: 2025 ICCAD CAD Contest Problem A: Hardware Trojan Detection on Gate-Level Netlist. | Chung-Han Chou, Chih-Jen (Jacky) Hsu, Hung-Chun Chiu, Kai-Chiang Wu, Yu-Guang Chen, Zhuo Li |
| 2025 | ICLR | Palu: KV-Cache Compression with Low-Rank Projection. | Chi-Chih Chang, Wei-Cheng Lin, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Mohamed S. Abdelfattah, Kai-Chiang Wu |
| 2025 | ICLR | Quamba: A Post-Training Quantization Recipe for Selective State Space Models. | Hung-Yueh Chiang, Chi-Chih Chang, Natalia Frumkin, Kai-Chiang Wu, Diana Marculescu |
| 2025 | ICML | Quamba2: A Robust and Scalable Post-training Quantization Framework for Selective State Space Models. | Hung-Yueh Chiang, Chi-Chih Chang, Natalia Frumkin, Kai-Chiang Wu, Mohamed S. Abdelfattah, Diana Marculescu |
| 2024 | CVPR | ELSA: Exploiting Layer-wise N: M Sparsity for Vision Transformer Acceleration. | Ning-Chi Huang, Chi-Chih Chang, Wei-Cheng Lin, Endri Taka, Diana Marculescu, Kai-Chiang Wu |
| 2024 | DSN | Synergizing GCN and GAT for Hardware Trojan Detection and Localization. | Yu-Chen Hsiao, Chia-Heng Yen, Bo-Yang Ke, Kai-Chiang Wu |
| 2024 | ITC | Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant. | Shu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao |
| 2024 | WACV | FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. | Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu |
| 2024 | VTS | Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. | Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao |
| 2023 | ITC | Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. | Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao |
| 2023 | VTS | Outlier Detection for Analog Tests Using Deep Learning Techniques. | Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao |
| 2023 | VTS | Test Generation for Defect-Based Faults of Scan Flip-Flops. | Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao |
| 2022 | DATE | Improving Cell-Aware Test for Intra-Cell Short Defects. | Dong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu, Mango C.-T. Chao |
| 2022 | VTS | Rule Generation for Classifying SLT Failed Parts. | Ho-Chieh Hsu, Cheng-Che Lu, Shih-Wei Wang, Kelly Jones, Kai-Chiang Wu, Mango C.-T. Chao |
| 2021 | VTS | An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention. | Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu |
| 2021 | VTS | Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. | Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao |
| 2020 | VTS | CNN-based Stochastic Regression for IDDQ Outlier Identification. | Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao |
| 2019 | ASPDAC | Aging-aware chip health prediction adopting an innovative monitoring strategy. | Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang |
| 2019 | DATE | Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications. | Ning-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu |
| 2019 | IOLTS | ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience. | Kai-Chiang Wu, Wei-Tao Huang, Chiao-Yang Huang |
| 2019 | ITC | Methodology of Generating Timing-Slack-Based Cell-Aware Tests. | Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao |
| 2019 | VTS | Layout-Based Dual-Cell-Aware Tests. | Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee |
| 2018 | DATE | MAUI: Making aging useful, intentionally. | Kai-Chiang Wu, Tien-Hung Tseng, Shou-Chun Li |
| 2017 | DATE | Analysis and optimization of variable-latency designs in the presence of timing variability. | Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu |
| 2017 | VTS | Fast WAT test structure for measuring Vt variance based on latch-based comparators. | Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao |
| 2012 | DATE | Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. | Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang |
| 2011 | DATE | Aging-aware timing analysis and optimization considering path sensitization. | Kai-Chiang Wu, Diana Marculescu |
| 2011 | ISLPED | Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. | Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang |
| 2010 | DATE | Clock skew scheduling for soft-error-tolerant sequential circuits. | Kai-Chiang Wu, Diana Marculescu |
| 2009 | DATE | Joint logic restructuring and pin reordering against NBTI-induced performance degradation. | Kai-Chiang Wu, Diana Marculescu |
| 2008 | ASPDAC | Soft error rate reduction using redundancy addition and removal. | Kai-Chiang Wu, Diana Marculescu |
| 2008 | ICCAD | Process variability-aware transient fault modeling and analysis. | Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marculescu |
| 2008 | ICCD | Power-aware soft error hardening via selective voltage scaling. | Kai-Chiang Wu, Diana Marculescu |
| 2006 | ASPDAC | Delay variation tolerance for domino circuits. | Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang |
| 2004 | DAC | Re-synthesis for delay variation tolerance. | Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu |