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Karam S. Chatha

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

32

Venues

9

Active years

1998–2012

Best venue rank

A*

Where they publish

Papers

32 indexed papers, newest first.

YearVenueTitleAuthors
2012DACUnrolling and retiming of stream applications onto embedded multicore processors.Weijia Che, Karam S. Chatha
2012DACSystem-level synthesis of memory architecture for stream processing sub-systems of a MPSoC.Glenn Leary, Weijia Che, Karam S. Chatha
2011DACCompilation of stream programs onto scratchpad memory based embedded multicore processors through retiming.Weijia Che, Karam S. Chatha
2010DACThermal aware task sequencing on embedded processors.Sushu Zhang, Karam S. Chatha
2010DATECompilation of stream programs for multicore processors that incorporate scratchpad memories.Weijia Che, Amrit Panda, Karam S. Chatha
2010ICCADScheduling of synchronous data flow models on scratchpad memory based embedded processors.Weijia Che, Karam S. Chatha
2010ICCDA lightweight run-time scheduler for multitasking multicore stream applications.Michael A. Baker, Karam S. Chatha
2010VLSIDDesign of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance.Glenn Leary, Karam S. Chatha
2009DACThroughput optimal task allocation under thermal constraints for multi-core processors.Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha
2009DATEPerformance optimal speed control of multi-core processors under thermal constraints.Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2009ICCADMaximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control.Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2009ISLPEDNear optimal battery-aware energy management.Sushu Zhang, Karam S. Chatha, Goran Konjevod
2008ASPDACAutomated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.Sushu Zhang, Karam S. Chatha
2008ICCADSystem-level thermal aware design of applications with uncertain execution time.Sushu Zhang, Karam S. Chatha
2007ASPDACApproximation Algorithm for Process Mapping on Network Processor Architectures.Christopher Ostler, Karam S. Chatha, Goran Konjevod
2007ASPDACApplication Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2007DACApproximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures.Christopher Ostler, Karam S. Chatha
2007DATEAn ILP formulation for system-level application mapping on network processor architectures.Christopher Ostler, Karam S. Chatha
2007ICCADApproximation algorithm for the temperature-aware scheduling problem.Sushu Zhang, Karam S. Chatha
2007ISLPEDApproximation algorithms for power minimization of earliest deadline first and rate monotonic schedules.Sushu Zhang, Karam S. Chatha, Goran Konjevod
2006DATEA low complexity heuristic for design of custom network-on-chip architectures.Krishnan Srinivasan, Karam S. Chatha
2005ASPDACSAGA: synthesis technique for guaranteed throughput NoC architectures.Krishnan Srinivasan, Karam S. Chatha
2005ICCADAn automated technique for topology and route generation of application specific on-chip interconnection networks.Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2005ISLPEDA technique for low energy mapping and routing in network-on-chip architectures.Krishnan Srinivasan, Karam S. Chatha
2005VLSIDA Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.Nagendran Rangan, Karam S. Chatha
2005VLSIDISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.Krishnan Srinivasan, Karam S. Chatha
2004DATEA Power and Performance Model for Network-on-Chip Architectures.Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha
2004ICCDLinear Programming based Techniques for Synthesis of Network-on-Chip Architectures.Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2004VLSIDAn ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.Krishnan Srinivasan, Karam S. Chatha
1999FPLHardware-Software Codesign for Dynamically Reconfigurable Architectures.Karam S. Chatha, Ranga Vemuri
1999RSPAn Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.Karam S. Chatha, Ranga Vemuri
1998RSPPerformance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns.Karam S. Chatha, Ranga Vemuri