Koji Nii
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
6
Active years
1990–2014
Best venue rank
A
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | DDECS | The LSI implementation of a memory based field programmable device for MCU peripherals. | Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda |
| 2011 | ISLPED | A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. | Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii |
| 2006 | ISLPED | A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. | Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2005 | ICCAD | Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. | Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara |
| 2005 | ISCAS | A 3224-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. | Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino |
| 1998 | ISLPED | A low power SRAM using auto-backgate-controlled MT-CMOS. | Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano |
| 1992 | ITC | LSSD Compatible and Concurrently Testable Ram. | Hideshi Maeno, Koji Nii, S. Sakayanagi, S. Kato |
| 1990 | ICCD | A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. | Masaki Hashizume, Takeomi Tamesada, Koji Nii |