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Kolin Paul

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

51

Venues

19

Active years

1999–2024

Best venue rank

National

Where they publish

Papers

51 indexed papers, newest first.

YearVenueTitleAuthors
2024HealthComDetection of Coronary Artery Disease Using PCG Signals for Wearable Devices: LSTM-Based Approach.Priyanka Chauhan, Kolin Paul
2024IJCNNMMTS: Multi-Modal Time Series Based Decision Support System for Ventilator Associated Pneumonia.Nikki Tiwari, Kolin Paul, Shrawan Kumar Raut, Animesh Ray, Surabhi Vyas, Naveet Wig
2024VLSIDLLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore.Avishek Choudhury, Brototi Mondal, Kolin Paul, Biplab K. Sikdar
2024VLSIDLong Short Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring.Vijay Kumar, Goldy, Kolin Paul, Mahesh Chowdhary
2022DATESACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators.Saurabh Tewari, Anshul Kumar, Kolin Paul
2021DSDScheduling Persistent and Fully Cooperative Instructions.Yu Yang, Ahmed Hemani, Kolin Paul
2021FCCMScheduling Persistent and Fully Cooperative Instructions.Yu Yang, Ahmed Hemani, Kolin Paul
2021NCAGlobal Monitor using SpatioTemporally Correlated Local Monitors.Geeta Yadav, Kolin Paul
2020AINADetection and Mitigation of LFA Attack in SDN-IoT Network.Alaa M. Allakany, Geeta Yadav, Kolin Paul, Koji Okamura
2020DDECSA Security Verification Template to Assess Cache Architecture Vulnerabilities.Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil
2019DSDGRanDE: Graphical Representation and Design Space Exploration of Embedded Systems.Rajesh Kedia, M. Balakrishnan, Kolin Paul
2019ETFAPatchRank: Ordering updates for SCADA systems.Geeta Yadav, Kolin Paul
2019ETFAAssessment of SCADA System Vulnerabilities.Geeta Yadav, Kolin Paul
2019IOLTSPASCAL: Timing SCA Resistant Design and Verification Flow.Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
2019VLSIDMajority Logic: Prime Implicants and n-Input Majority Term Equivalence.Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2018HPCCDAPP: Accelerating Training of DNN.Sapna Sapna, N. S. Sreenivasalu, Kolin Paul
2016HPCCGAMS: Genome Assembly on Multi-GPU Using String Graph.Gaurav Jain, Lalchand Rathore, Kolin Paul
2014DSDMorphable Compression Architecture for Efficient Configuration in CGRAs.Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen
2014DSDHigh Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
2014FCCMCustomizable Compression Architecture for Efficient Configuration in CGRAs.Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen
2014FCCMMapping Tasks to a Dynamically Reconfigurable Coarse Grained Array.Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan
2014FPLTransPar: Transformation based dynamic Parallelism for low power CGRAs.Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2014HPCCEnergy Efficient Dynamic Core Allocation for Video Decoding in Embedded Multicore Architectures.Rajesh Kumar Pal, Kolin Paul, Sanjiva Prasad
2014ICARCVAn event-triggered based robust control of robot manipulator.Niladri Sekhar Tripathy, I. N. Kar, Kolin Paul
2014VLSIDAccelerating Genome Assembly Using Hard Embedded Blocks in FPGAs.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
2013COMSNETSProvenance framework for mHealth.Aarathi Prasad, Ronald A. Peterson, Shrirang Mare, Jacob Sorber, Kolin Paul, David Kotz
2013DSDDistributed Runtime Computation of Constraints for Multiple Inner Loops.Nasim Farahini, Ahmed Hemani, Kolin Paul
2013DSDEnergy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
2013FCCMFAssem: FPGA Based Acceleration of De Novo Genome Assembly.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier
2013HiPCGAGM: Genome assembly on GPU using mate pairs.Ashutosh Jain, Anshuj Garg, Kolin Paul
2013HPCCGGAKE: GPU Based Genome Assembly Using K-Mer Extension.Anshuj Garg, Ashutosh Jain, Kolin Paul
2013ISCASHigh performance 3D-FFT implementation.U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar
2013VLSIDAccelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
2012DSDEnergy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes.Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2012DSDreMORPH: A Runtime Reconfigurable Architecture.Kolin Paul, Chinmaya Dash, Mansureh Shahraki Moghaddam
2012ISPAReKonf: A Reconfigurable Adaptive ManyCore Architecture.Rajesh Kumar Pal, Kolin Paul, Sanjiva Prasad
2011VLSIDImproving Android Performance and Energy Efficiency.Tapas Kumar Kundu, Kolin Paul
2011VLSIDA Reconfigurable Processor for Phylogenetic Inference.Pei Liu, Ahmed Hemani, Kolin Paul
2010ASPDACA high-level synthesis flow for custom instruction set extensions for application-specific processors.Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul
2010VLSIDClocking-Based Coplanar Wire Crossing Scheme for QCA.Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
2008VLSIDExhaustive Enumeration of Legal Custom Instructions for Extensible Processors.Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2008VLSIDA Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2007DSDSilicon Compaction/Defragmentation for Partial Runtime Reconfiguration.Kolin Paul, Jol Porquet, Josep Llosa
2007VLSIDApplication Specific Datapath Extension with Distributed I/O Functional Units.Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2000VLSIDTheory and Applications of Cellular Automata for VLSI Design and Testing.Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar
2000VLSIDApplication of GF(2p) CA in Burst Error Correcting Codes.Kolin Paul, Dipanwita Roy Chowdhury
2000VLSIDScalable Pipelined Micro-Architecture for Wavelet Transform.Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury
2000VLSIDGF(2p) CA Based Vector Quantization for Fast Encoding of Still Images.Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury
2000VLSIDTheory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee
1999HiPCCellular Automata Based Transform Coding for Image Compression.Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
1999VLSIDA VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata.Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri