| 2026 | DDECS | Assessing the Vulnerability of Open-Source RISC-V Processors to Transient Execution Attacks. | Elia Lazzeri, Gianluca Furano, Luca Cassano |
| 2026 | ETS | A real opportunity or still a promise? The current status of the RISC-V ecosystem. | Elia Lazzeri, Gianluca Furano, Luca Cassano |
| 2026 | IOLTS | Reality Check for RISC-V: Assessing Software Maturity, Performance and Security. | Elia Lazzeri, Gianluca Furano, Luca Cassano |
| 2025 | DDECS | S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors. | Elia Lazzeri, Matteo Colella, Gianluca Furano, Luca Cassano |
| 2025 | ITC | A Benchmark Suite to Evaluate DNN's Resilience. | Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passariello, Annachiara Ruospo, Ernesto Snchez, Matteo Sonza Reorda, Vittorio Turco |
| 2024 | DATE | Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes. | Bruno Endres Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi |
| 2024 | ETS | Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. | Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini |
| 2023 | IOLTS | Towards Dependable RISC-V Cores for Edge Computing Devices. | Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola |
| 2022 | DDECS | Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? | Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena-Ioana Vatajelu |
| 2022 | DDECS | On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors. | Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale |
| 2020 | DATE | An Approximation-based Fault Detection Scheme for Image Processing Applications. | Matteo Biasielli, Luca Cassano, Antonio Miele |
| 2020 | IOLTS | Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs. | Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele |
| 2020 | IOLTS | Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis. | Ana Lasheras, Ramon Canal, Eva Rodrguez, Luca Cassano |
| 2019 | DATE | A Smart Fault Detection Scheme for Reliable Image Processing Applications. | Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Antonio Miele |
| 2019 | IOLTS | HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems. | Cristiana Bolchini, Luca Cassano, Ivan Montalbano, Giampiero Repole, Andrea Zanetti, Giorgio Di Natale |
| 2016 | DATE | Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis. | Cristiana Bolchini, Luca Cassano, Antonio Miele |
| 2014 | DATE | Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations. | Daniel Cesarini, Luca Cassano, Alessio Fagioli, Marco Avvenuti |
| 2014 | ETS | A novel adaptive fault tolerant flip-flop architecture based on TMR. | Luca Cassano, Alberto Bosio, Giorgio Di Natale |
| 2014 | IOLTS | Early assessment of SEU sensitivity through untestable fault identification. | Luca Cassano, Hiplito Guzmn-Miranda, Miguel A. Aguirre |
| 2014 | ITC | Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs. | Luca Cassano |
| 2013 | DATE | On-line testing of permanent radiation effects in reconfigurable systems. | Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone |
| 2013 | IECON | Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries. | Federico Baronti, Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Roberto Roncella, Roberto Saletti |
| 2012 | IOLTS | SEU-X: A SEu un-excitability prover for SRAM-FPGAs. | Cinzia Bernardeschi, Luca Cassano, Andrea Domenici |
| 2011 | DDECS | Failure probability of SRAM-FPGA systems with Stochastic Activity Networks. | Cinzia Bernardeschi, Luca Cassano, Andrea Domenici |
| 2011 | FPL | Failure Probability and Fault Observability of SRAM-FPGA Systems. | Cinzia Bernardeschi, Luca Cassano, Andrea Domenici |