Luis Entrena
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
39
Venues
11
Active years
1993–2022
Best venue rank
A*
Where they publish
Papers
39 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ETS | Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. | Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo |
| 2018 | IOLTS | A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. | Honorio Martn, Luis Entrena, Sophie Dupuis, Giorgio Di Natale |
| 2014 | IOLTS | A new solution to on-line detection of Control Flow Errors. | Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-Garca, Almudena Lindoso, Luis Entrena |
| 2014 | IOLTS | Error masking with approximate logic circuits using dynamic probability estimations. | Antonio Sanchez-Clemente, Luis Entrena, Mario Garca-Valderas |
| 2013 | IOLTS | Exploiting the debug interface to support on-line test of control flow errors. | Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-Garca, Almudena Lindoso, Luis Entrena |
| 2012 | IOLTS | SEU sensitivity of robust communication protocols. | Celia Lpez-Ongil, Marta Portela-Garca, Mario Garca-Valderas, Anna Vaskova, Luis Entrena, Joaqun Rivas-Abalo, Alberto Martn-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego |
| 2012 | IOLTS | Logic masking for SET Mitigation Using Approximate Logic Circuits. | Antonio Sanchez-Clemente, Luis Entrena, Mario Garca-Valderas, Celia Lpez-Ongil |
| 2011 | IOLTS | AKARI-X: A pseudorandom number generator for secure lightweight systems. | Honorio Martn, Enrique San Milln, Luis Entrena, Julio Csar Hernndez Castro, Pedro Peris-Lopez |
| 2011 | IOLTS | Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. | Anna Vaskova, Celia Lpez-Ongil, Mario Garca-Valderas, Marta Portela-Garca, Luis Entrena |
| 2011 | IOLTS | Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. | Anna Vaskova, Celia Lpez-Ongil, Enrique San Milln, Alejandro Jimnez-Horas, Luis Entrena |
| 2010 | IOLTS | An on-line fault detection technique based on embedded debug features. | Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-Garca, Mario Garca-Valderas, Celia Lpez-Ongil, Luis Entrena |
| 2010 | IOLTS | Robust cryptographic ciphers with on-line statistical properties validation. | Anna Vaskova, Celia Lpez-Ongil, Alejandro Jimnez-Horas, Enrique San Milln, Luis Entrena |
| 2009 | IOLTS | In-depth analysis of digital circuits against soft errors for selective hardening. | Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena |
| 2009 | IOLTS | Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. | Alejandro Jimnez-Horas, Enrique San Milln, Celia Lpez-Ongil, Marta Portela-Garca, Mario Garca-Valderas, Luis Entrena |
| 2009 | IOLTS | Briefing power/reliability optimization in embedded software design. | Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-Garca, Celia Lpez-Ongil, Mario Garca-Valderas, Luis Entrena |
| 2008 | DSD | Logic Transformations by Multiple Wire Network Addition. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2008 | FPL | Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. | Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez |
| 2008 | IOLTS | Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. | Celia Lpez-Ongil, Alejandro Jimnez-Horas, Marta Portela-Garca, Mario Garca-Valderas, Enrique San Milln, Luis Entrena |
| 2007 | CAIP | Wavelet-Based Fingerprint Region Selection. | Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez |
| 2007 | IOLTS | A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. | Marta Portela-Garca, Celia Lpez-Ongil, Mario Garca-Valderas, Luis Entrena |
| 2006 | ETS | Fault Injection-based Reliability Evaluation of SoPCs. | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena |
| 2006 | IOLTS | Emulation-based Fault Injection in Circuits with Embedded Memories. | Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena |
| 2004 | ECCV | Architectures for Biometric Match-on-Token Solutions. | Raul Snchez-Reillo, Judith Liu-Jimenez, Luis Entrena |
| 2004 | FPL | FPGA Implementation of Biometric Authentication System Based on Hand Geometry. | Celia Lpez-Ongil, Raul Snchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Snchez, Luis Entrena |
| 2004 | FPL | Power Consumption Reduction Through Dynamic Reconfiguration. | Michael G. Lorenz, Luis Mengibar, Mario Garca-Valderas, Luis Entrena |
| 2004 | IOLTS | Transient Fault Emulation of Hardened Circuits in FPGA Platforms. | Mario Garca-Valderas, Celia Lpez-Ongil, Marta Portela-Garca, Luis Entrena |
| 2003 | FPL | Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. | Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Snchez-Reillo |
| 2002 | DATE | New Techniques for Speeding-Up Fault-Injection Campaigns. | Luis Berrojo, Isabel Gonzlez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia Lpez |
| 2002 | IOLTS | Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. | Luis Berrojo, Isabel Gonzlez, Luis Entrena, Celia Lpez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero |
| 2002 | VTS | An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. | Luis Berrojo, Isabel Gonzlez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia Lpez |
| 2001 | ASPDAC | Functional extension of structural logic optimization techniques. | Jos Alberto Espejo, Luis Entrena, Enrique San Milln, Emilio Olas |
| 2001 | DATE | Generalized reasoning scheme for redundancy addition and removal logic optimization. | Jos Alberto Espejo, Luis Entrena, Enrique San Milln, Emilio Olas |
| 2001 | DSD | On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | ICCAD | On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | IOLTS | Automatic Insertion of Fault-Tolerant Structures at the RT Level. | Luis Entrena, Celia Lpez, Emilio Olas |
| 2001 | IOLTS | Logic Optimization of Unidirectional Circuits with Structural Methods. | Luis Entrena, Celia Lpez, Emilio Olas, Enrique San Milln, Jos Alberto Espejo |
| 1999 | DATE | Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo, Silvia Chiusano, Fulvio Corno |
| 1995 | RSP | VHDL virtual prototyping. | Serafn Olcoz, Luis Entrena, Luis Berrojo |
| 1993 | ICCAD | Sequential logic optimization by redundancy addition and removal. | Luis Entrena, Kwang-Ting Cheng |