| 2026 | EuroPar | Accelerating Multi-agent Reinforcement Learning on Heterogeneous Platforms. | Samuel Wiggins, Grace Zgheib, Mahesh A. Iyer, Viktor Prasanna |
| 2026 | HPDC | FAME: A Framework for Accelerating Independent Multi-Agent Reinforcement Learning on Heterogeneous Platforms. | Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna |
| 2025 | EuroPar | Accelerating Independent Multi-Agent Reinforcement Learning on Multi-GPU Platforms. | Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna |
| 2025 | FCCM | A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. | Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib |
| 2025 | FPL | Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. | Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah |
| 2025 | ICPADS | ARC: A Runtime Engine for Accelerating Independent Multi-Agent Reinforcement Learning on Multi-Core Processors. | Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna |
| 2024 | FPL | Better Together: Combining Analytical and Annealing Methods for FPGA Placement. | Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan |
| 2024 | FPL | A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning. | Samuel Wiggins, Yuan Meng, Mahesh A. Iyer, Viktor K. Prasanna |
| 2022 | ASPDAC | DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. | Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan |
| 2020 | ASPDAC | High-Definition Routing Congestion Prediction for Large-Scale FPGAs. | Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2020 | FPGA | Symbiosis in Action: Reconfigurable Architectures and EDA. | Mahesh A. Iyer |
| 2019 | ASPDAC | A shape-driven spreading algorithm using linear programming for global placement. | Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2019 | FPL | FPGA Accelerated FPGA Placement. | Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2017 | DAC | LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. | Love Singhal, Mahesh A. Iyer, Saurabh N. Adya |
| 2016 | ICCAD | Detailed placement for modern FPGAs using 2D dynamic programming. | Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan |
| 2003 | ITC | Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. | Mahesh A. Iyer |
| 1999 | DATE | Wavefront Technology Mapping. | Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer |
| 1999 | ICCD | A Robust Solution to the Timing Convergence Problem in High-Performance Design. | Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking |
| 1999 | ITC | High Time For High Level ATPG. | Mahesh A. Iyer |
| 1996 | DAC | Identifying Sequential Redundancies Without Search. | Mahesh A. Iyer, David E. Long, Miron Abramovici |
| 1996 | DATE | Surprises in Sequential Redundancy Identification. | Mahesh A. Iyer, David E. Long, Miron Abramovici |
| 1995 | VTS | Identifying sequentially untestable faults using illegal states. | David E. Long, Mahesh A. Iyer, Miron Abramovici |
| 1994 | ITC | Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). | Mahesh A. Iyer, Miron Abramovici |
| 1994 | VLSID | Low-Cost Redundancy Identification for Combinatorial Circuits. | Mahesh A. Iyer, Miron Abramovici |
| 1992 | ITC | One-Pass Redundancy Identification and Removal. | Miron Abramovici, Mahesh A. Iyer |