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Martin Omaa

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

25

Venues

6

Active years

2003–2026

Best venue rank

C

Where they publish

Papers

25 indexed papers, newest first.

YearVenueTitleAuthors
2026IOLTSReliability of Multilevel Cell Phase-Change Memories for AI Implementations.G. Settegrani, R. Gattoni, Sara Cret, Matteo Naldi, Martin Omaa, Cecilia Metra, I. S. Troja
2025IOLTSOn-Line Test of Fully Integrated Voltage Regulators for High Performance Microprocessors of Autonomous Systems.Martin Omaa, A. Menghi, A. Stefani, E. Vicini, Cecilia Metra, G. Froio, S. Petrucci
2024IOLTSSilent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches.Martin Omaa, A. Manfredi, Cecilia Metra, R. Locatelli, M. Chiavacci, S. Petrucci
2024IOLTSReliability of AI in Predicting the State of Health of Li-Ion BatteriesSara Cret, Martin Omaa, Cecilia Metra, Gianni Borelli
2024IOLTSOn the Reliability of Clock Monitoring Units for Safety Critical Applications' Microcontrollers.Massimiliano Zhupa, Matteo Naldi, Martin Omaa, Cecilia Metra
2022IOLTSNovel BTI Robust Ring-Oscillator-Based Physically Unclonable Function.Marco Grossi, Martin Omaa, Daniele Rossi, Biagio Marzulli, Cecilia Metra
2016DATEInverters' self-checking monitors for reliable photovoltaic systems.Martin Omaa, A. Fiore, Cecilia Metra
2013ETSNovel approach to reduce power droop during scan-based logic BIST.Martin Omaa, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, R. Galivache
2008ETSFunction-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.Cecilia Metra, Daniele Rossi, Martin Omaa, Abhijit Jas, Rajesh Galivanche
2007ITCNovel compensation scheme for local clocks of high performance microprocessors.Cecilia Metra, Martin Omaa, T. M. Mak, Simon Tam
2007VTSNovel Approach to Clock Fault Testing for High Performance Microprocessors.Cecilia Metra, Martin Omaa, T. M. Mak, Simon Tam
2006DATELow-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.Martin Omaa, Jos Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2006DDECSCan Clock Faults be Detected Through Functional Test?Cecilia Metra, Daniele Rossi, Martin Omaa, Jos Manuel Cazeaux, T. M. Mak
2006IOLTSPath (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.Cecilia Metra, Martin Omaa, Daniele Rossi, Jos Manuel Cazeaux, T. M. Mak
2006IOLTSChecker No-Harm Alarm Robustness.Daniele Rossi, Martin Omaa, Cecilia Metra, Andrea Pagni
2005IOLTSOn Transistor Level Gate Sizing for Increased Robustness to Transient Faults.Jos Manuel Cazeaux, Daniele Rossi, Martin Omaa, Cecilia Metra, Abhijit Chatterjee
2005IOLTSOn the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.Martin Omaa, O. Losco, Cecilia Metra, Andrea Pagni
2005VTSLow Cost Scheme for On-Line Clock Skew Compensation.Martin Omaa, Daniele Rossi, Cecilia Metra
2004DATEAre Our Design for Testability Features Fault Secure?Cecilia Metra, T. M. Mak, Martin Omaa
2004IOLTSLow-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.Jos Manuel Cazeaux, Martin Omaa, Cecilia Metra
2004IOLTSHardware Reconfiguration Scheme for High Availability Systems.Cecilia Metra, A. Ferrari, Martin Omaa, Andrea Pagni
2004ITCRisks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.Cecilia Metra, T. M. Mak, Martin Omaa
2003DATEHigh Speed and Highly Testable Parallel Two-Rail Code Checker.Martin Omaa, Daniele Rossi, Cecilia Metra
2003IOLTSA Model for Transient Fault Propagation in Combinatorial Logic.Martin Omaa, Giacinto Papasso, Daniele Rossi, Cecilia Metra
2003ITCNovel Transient Fault Hardened Static Latch.Martin Omaa, Daniele Rossi, Cecilia Metra