| 2026 | DATE | Smart Imager with Object Detection Exploiting Edge-Frame-Base Processing and Bounding Box Extraction for μW Power Purely-Harvested Sensor Nodes. | Hayate Okuhara, Udari De Alwis, Liu Yue, Karim Ali Ahmed, Massimo Alioto |
| 2024 | ISCAS | A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems. | Marco Privitera, Andrea Ballo, Alfio Dario Grasso, Massimo Alioto |
| 2021 | ISCAS | STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks. | Thi-Nhan Pham, Kien Trinh Quang, Ik-Joon Chang, Massimo Alioto |
| 2020 | ISCAS | Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide-Voltage Scaling. | Saurabh Jain, Longyang Lin, Massimo Alioto |
| 2020 | ISCAS | Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm. | Sachin Taneja, Massimo Alioto |
| 2019 | ISCAS | Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic. | Orazio Aiello, Paolo Crovetti, Massimo Alioto |
| 2018 | ACSSC | Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding. | Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas |
| 2018 | DATE | Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. | Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto |
| 2018 | FIE | Project-Based Learning in Digital Fundamentals Course Using FPGAs. | Dingjuan Chua, Jieyi Gao, Massimo Alioto, Yong Ping Xu, Sangit Sasidhar |
| 2018 | ISCAS | Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V. | Orazio Aiello, Paolo Crovetti, Massimo Alioto |
| 2018 | ISCAS | Novel Time-Based Sensing Scheme for STT-MRAMs. | Kien Trinh Quang, Sergio Ruocco, Massimo Alioto |
| 2018 | ISCAS | Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. | Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto |
| 2017 | DATE | Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing. | Massimo Alioto |
| 2017 | ISCAS | Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric. | Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti |
| 2017 | ISCAS | Power-precision scalable latch memories. | Darjn Esposito, Antonio G. M. Strollo, Massimo Alioto |
| 2017 | ISCAS | Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers. | Longyang Lin, Kien Trinh Quang, Massimo Alioto |
| 2017 | ISCAS | A variation-aware simulation framework for hybrid CMOS/spintronic circuits. | Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto |
| 2016 | ISCAS | Boosted sensing for enhanced read stability in STT-MRAMs. | Kien Trinh Quang, Sergio Ruocco, Massimo Alioto |
| 2016 | ISCAS | STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling. | Kien Trinh Quang, Sergio Ruocco, Massimo Alioto |
| 2015 | ISCAS | Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance. | Kien Trinh Quang, Sergio Ruocco, Massimo Alioto |
| 2015 | ISCAS | Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. | Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici |
| 2015 | ISCAS | AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. | Wenfeng Zhao, Yajun Ha, Massimo Alioto |
| 2013 | VTS | New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond. | Bozena Kaminska, Bernard Courtois, Massimo Alioto |
| 2012 | ISCAS | A simple keeper topology to reduce delay variations in nanometer domino logic. | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
| 2011 | ISCAS | DET FF topologies: A detailed investigation in the energy-delay-area domain. | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
| 2011 | ISCAS | A novel back-biasing low-leakage technique for FinFET forced stacks. | Davide Baccarin, David Esseni, Massimo Alioto |
| 2011 | ISCAS | Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. | Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jrme Mitard, Liesbeth Witters, Thomas Y. Hoffmann |
| 2011 | ISCAS | Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations. | Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto |
| 2011 | ISCAS | Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. | Fabio Frustaci, Pasquale Corsonello, Massimo Alioto |
| 2010 | ISCAS | Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits. | Massimo Alioto |
| 2010 | ISCAS | Analysis of layout density in FinFET standard cells and impact of fin technology. | Massimo Alioto |
| 2010 | ISCAS | Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. | Massimo Alioto, Paolo Bennati, Roberto Giorgi |
| 2010 | ISCAS | Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
| 2010 | ISCAS | Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits. | Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer |
| 2010 | ISCAS | Design metrics for RTL level estimation of delay variability due to intradie (random) variations. | Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto |
| 2009 | ISCAS | Understanding Loading Effects of RC Uniform Interconnects. | Massimo Alioto |
| 2009 | ISCAS | Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. | Massimo Alioto, Stphane Badel, Yusuf Leblebici |
| 2009 | ISCAS | Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
| 2009 | ISCAS | Analysis and Design of Ultra-low Power Subthreshold MCML Gates. | Massimo Alioto, Yusuf Leblebici |
| 2008 | ISCAS | Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. | Massimo Alioto, Luca Fondelli, Santina Rocchi |
| 2008 | ISCAS | Power-delay optimization in MCML tapered buffers. | Massimo Alioto, Gaetano Palumbo |
| 2008 | ISCAS | Explicit energy evaluation in RLC tree circuits with ramp inputs. | Massimo Alioto, Massimo Poli, Gaetano Palumbo |
| 2008 | ISCAS | A general model for differential power analysis attacks to static logic circuits. | Massimo Alioto, Massimo Poli, Santina Rocchi |
| 2008 | ISCAS | Improving the power-delay product in SCL circuits using source follower output stage. | Armin Tajalli, Frank K. Grkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer |
| 2007 | ISCAS | Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
| 2007 | ISCAS | High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. | Massimo Alioto, Gaetano Palumbo |
| 2007 | ISCAS | Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. | Massimo Alioto, Gaetano Palumbo |
| 2007 | ISCAS | Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. | Massimo Alioto, Gaetano Palumbo |
| 2007 | ISCAS | Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
| 2006 | ISCAS | A technique to design high entropy chaos-based true random bit generators. | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
| 2006 | ISCAS | Delay uncertainty due to supply variations in static and dynamic full adders. | Massimo Alioto, Gaetano Palumbo |
| 2006 | ISCAS | Nanometer MCML gates: models and design considerations. | Massimo Alioto, Gaetano Palumbo |
| 2006 | ISCAS | Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
| 2006 | ISCAS | Analysis and design of MCML gates with hysteresis. | Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli |
| 2005 | ISCAS | Long period pseudo random bit generators derived from a discretized chaotic map. | Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli |
| 2005 | ISCAS | An approach to the design of PFSCL gates. | Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli |
| 2005 | ISCAS | Design techniques for low-power cascaded CML gates. | Massimo Alioto, Gaetano Palumbo |
| 2004 | ISCAS | Positive-Feedback Source-Coupled Logic: a delay model. | Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli |
| 2004 | ISCAS | A gate-level strategy to design Carry Select Adders. | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
| 2003 | ISCAS | Design of MUX, XOR and D-latch SCL gates. | Massimo Alioto, Gaetano Palumbo |
| 2002 | ISCAS | Power-delay trade-offs in SCL gates. | Massimo Alioto, Gaetano Palumbo |
| 2001 | ISCAS | CML ring oscillators: oscillation frequency. | Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo |
| 2000 | ISCAS | Evaluation of power consumption in adiabatic circuits. | Massimo Alioto, Gaetano Palumbo |
| 2000 | ISCAS | High-speed bipolar MUX modeling and design. | Massimo Alioto, Gaetano Palumbo |